74AHCT377PW,112 NXP Semiconductors, 74AHCT377PW,112 Datasheet - Page 4

• Manufacturer Part Number: 74AHCT377PW,112
• Description: IC OCTAL D F-F POS-EDGE 20-TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74AHCTr
• Type: D-Type Busr

Specifications of 74AHCT377PW,112

• Package / Case: 20-TSSOP
• Function: Standard
• Output Type: Non-Inverted
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Frequency - Clock: 130MHz
• Delay Time - Propagation: 5.7ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 8mA, 8mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 1
• Logic Family: AHCT
• Logic Type: D-Type Edge Triggered Flip-Flop
• Polarity: Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 4 ns
• High Level Output Current: - 8 mA
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 4.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2521-5; 935267993112

NXP Semiconductors
5. Pinning information
Table 2.
74AHC_AHCT377_2
Product data sheet
Symbol
E
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
CP
Q4
D4
D5
Q5
Q6
D6
D7
Q7
V
Fig 5.
CC
Pin configuration SO20 and TSSOP20
Pin description
5.1 Pinning
5.2 Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Description
data enable input (active LOW)
flip-flop output
data input
data input
flip-flop output
flip-flop output
data input
data input
flip-flop output
ground (0 V)
clock input (LOW-to-HIGH, edge triggered)
flip-flop output
data input
data input
flip-flop output
flip-flop output
data input
data input
flip-flop output
supply voltage
GND
Q0
Q1
Q2
Q3
D0
D1
D2
D3
E
Rev. 02 — 12 June 2008
10
1
2
3
4
5
6
7
8
9
Octal D-type flip-flop with data enable; positive-edge trigger
377
mna917
74AHC377; 74AHCT377
20
19
18
17
16
15
14
13
12
11
V
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
CC
© NXP B.V. 2008. All rights reserved.
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