si8405 Silicon Laboratories, si8405 Datasheet - Page 20

• Manufacturer Part Number: si8405
• Description: Bidirectional I 2c Isolators With Unidirectional Digital Channels
• Manufacturer: Silicon Laboratories

Si840x
5.3. I
Table 13 lists the design constraints.
5.4. I
The first step in applying an I
Ideally, it should be the side which:
1. Is compatible with the range of bus pull up specified by the manufacturer. For example, the Si8400/05 isolators
2. Has the highest input low level for devices on the bus. Some devices may specify an input low of 0.8 V and
3. Have devices on the bus that can pull down below the isolator input low level. For example, the Si840x input
4. Has the lowest noise. Due to the special logic levels, noise margins can be as low as 50 mV.
Although I
having a standard TTL logic low level of 0.8 V. In this case, use the lowest recommended bus pull-up. In this case,
the Si8400/05 input low level will be reduced from 0.9 V maximum to 0.83 V maximum. It is important to take into
account the input level negative temperature coefficient to ensure adequate noise margin. For example, if the bus
device is specified for a maximum input low level of 0.8 V at 85 °C, the typical –0.6 mV/C temperature coefficient
means that at –40 °C the input level will be 0.875 V minimum. This results in a noise margin of 45 mV.
20
Design Constraint
To prevent the latch condition, the
isolator output low level must be
greater than the isolator input high
level.
The bus output low must be less
than the isolator input low logic
level.
The isolator output low must be
greater than the bus input low.
are normally used with a pull up of 0.5 mA to 3 mA.
other devices might require an input low of 0.3 x Vdd. Assuming a 3.3 V minimum power supply, the side with
an input low of 0.3 x Vdd is the better side because this side has an input low level of 1.0 V.
level is 0.545 V. As most CMOS devices can pull to within 0.4 V of GND this is generally not an issue.
2
2
C Isolator Design Constraints
C Isolator Design Considerations
2
C isolators typically have an output low of 0.9 V, it is still possible to connect the isolator A side to a bus
2
C isolator is to choose which side of the bus will be connected to the isolator A side.
Bus V
ΔVSDA1, ΔVSCL1 = 50 mV minimum
Table 13. Design Constraints
Isolator V
Isolator V
Input/Output Logic Low Level
Bus V
IL
Isolator V
Isolator V
0.3 x V
Data Sheet Values
Preliminary Rev. 0.1
OL
IL
V
OL
Difference
DD
DD
= 0.4 V maximum
= 0.545 V minimum
OL
= 0.9 V maximum
IL
= 1.0 V minimum for
= 3.3 V
0.6 V typical
0.8 V typical
This is normally guaranteed by the
isolator data sheet. However, if the
pull up strength is too weak, the out-
put low voltage will fall and can get
too close to the input low logic level.
These track over temperature.
If the pull up strength is too large,
the devices on the bus might not pull
the voltage below the input low
range. These have opposite temper-
ature coefficients. Worst case is hot
temperature.
If the pull up strength is too large,
the isolator might not pull below the
bus input low voltage.
Si8400/05 Vol: –1.8 mV/C
CMOS buffer: –0.6 mV/C
This provides some temperature
tracking, but worst case is cold tem-
perature.
Effect of Bus Pull-up Strength
and Temperature