st20-gp1 STMicroelectronics, st20-gp1 Datasheet - Page 32

• Manufacturer Part Number: st20-gp1
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP1
On start-up, the Mask register is initialized to zero’s, thus all interrupts are disabled, both globally
and individually. When a 1 is written to the GlobalEnable bit, the individual interrupt bits are still
disabled and must also have a 1 individually written to the InterruptEnable bit to enable the
respective interrupt.
The Mask register is mapped onto two additional addresses so that bits can be set or cleared
individually.
Set_Mask (address ‘interrupt base address + #C4’) allows bits to be set individually. Writing a ‘1’ in
this register sets the corresponding bit in the Mask register, a ‘0’ leaves the bit unchanged.
Clear_Mask (address ‘interrupt base address + #C8’) allows bits to be cleared individually. Writing
a ‘1’ in this register resets the corresponding bit in the Mask register, a ‘0’ leaves the bit
unchanged.
Pending register
The Pending register contains a bit per interrupt with each bit controlled by the corresponding
interrupt. A read can be used to examine the state of the interrupt controller while a write can be
used to explicitly trigger an interrupt.
A bit is set when the triggering condition for an interrupt is met. All bits are independent so that
several bits can be set in the same cycle. Once a bit is set, a further triggering condition will have
no effect. The triggering condition is independent of the Mask register.
The highest priority interrupt bit is reset once the interrupt controller has made an interrupt request
to the CPU.
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Mask
Bit
0
1
2
3
4
16
15:5
Bit field
Interrupt0Enable
Interrupt1Enable
Interrupt2Enable
Interrupt3Enable
Interrupt4Enable
GlobalEnable
Interrupt controller base address + #C0
Function
When set to 1, interrupt 0 is enabled. When 0, interrupt 0 is disabled.
When set to 1, interrupt 1 is enabled. When 0, interrupt 1 is disabled.
When set to 1, interrupt 2 is enabled. When 0, interrupt 2 is disabled.
When set to 1, interrupt 3 is enabled. When 0, interrupt 3 is disabled.
When set to 1, interrupt 4 is enabled. When 0, interrupt 4 is disabled.
When set to 1, the setting of the interrupt is determined by the specific InterruptEn-
able bit. When 0, all interrupts are disabled.
RESERVED. Write 0.
Table 5.3 Mask register format
Read/Write