t14m256a TM Technology Inc., t14m256a Datasheet - Page 7

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t14m256a

Manufacturer Part Number
t14m256a
Description
32k X 8 High Speed Cmos Static Ram
Manufacturer
TM Technology Inc.
Datasheet

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Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs
TM Technology Inc. reserves the right
to change products or specifications without notice.
2. The data output from
3.
4. Transition is measured
5. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of
should not be applied.
guaranteed but not 100% tested.
t WP or (t WHZ + t DW ) to allow the I/O drivers to turn off and data to be placed on the bus for the
required t DW . If
apply and the write pulse can be as short as the specified t WP .
D
CH
OUT
TE
provides the read data for the next address.
OE
D
OUT
is high during a
500 mV from steady state with
are the same as the data written to
WE
P. 7
controlled write cycle, this requirement does not
C
L
= 5pF. This parameter is
D
Publication Date: FEB. 2004
IN
during the write cycle.
T14M256A
Revision:H

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