st72321j STMicroelectronics, st72321j Datasheet - Page 30

• Manufacturer Part Number: st72321j
• Description: 8-bit Mcu With Nested Interrupts, Flash, 10-bit Adc, 5 Timers, Spi, Sci, I2c Interface
• Manufacturer: STMicroelectronics

ST72321J
7 INTERRUPTS
7.1 INTRODUCTION
The ST7 enhanced interrupt management pro-
vides the following features:
This interrupt management is based on:
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
– Fixed interrupt vector addresses located at the
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest-
ed) ST7 interrupt controller.
7.2 MASKING AND PROCESSING FLOW
The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
each interrupt vector (see
ing flow is shown in
Figure 16. Interrupt Processing Flowchart
30/179
high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.
Hardware interrupts
Software interrupt (TRAP)
Nested or concurrent interrupt management
with
management:
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 2 non maskable events: RESET, TRAP
flexible
RESTORE PC, X, A, CC
RESET
FROM STACK
interrupt
Figure 16
Table
priority
6). The process-
Y
and
INSTRUCTION
INTERRUPT
INSTRUCTION
FETCH NEXT
PENDING
EXECUTE
N
“IRET”
N
level
Y
When an interrupt request has to be serviced:
– Normal processing is suspended at the end of
– The PC, X, A and CC registers are saved onto
– I1 and I0 bits of CC register are set according to
– The PC is then loaded with the interrupt vector of
The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
Table 6. Interrupt Software Priority Levels
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
Interrupt software priority
the current instruction execution.
the stack.
the corresponding values in the ISPRx registers
of the serviced interrupt vector.
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).
STAYS PENDING
THE INTERRUPT
Interrupt has the same or a
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
lower software priority
than current one
STACK PC, X, A, CC
Level
High
Low
TRAP
I1:0
N
I1
1
0
0
1
Y
I0
0
1
0
1