st72324bk STMicroelectronics, st72324bk Datasheet - Page 59

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st72324bk

Manufacturer Part Number
st72324bk
Description
3 V/5 V Range 8-bit Mcu With 4/8 Kbyte Rom, 10-bit Adc, Four Timers And Spi
Manufacturer
STMicroelectronics
Datasheet

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ST72323 ST72323L
9.1.6
9.1.7
9.1.8
9.1.9
Table 29.
Hardware watchdog option
If hardware watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the WDGCR is not used. Refer to the Option byte description.
Using Halt mode with the WDG (WDGHALT option)
The following recommendation applies if Halt mode is used when the watchdog is enabled.
Interrupts
None.
Register description
Control register (WDGCR)
Reset Value: 0111 1111 (7Fh)
Mode
Slow
Wait
Halt
WDGA
Before executing the Halt instruction, refresh the WDG counter, to avoid an unexpected
WDG reset immediately after waking up the microcontroller.
7
No effect on Watchdog.
No effect on Watchdog.
OIE bit in
MCCSR
register
0
0
1
Low-power modes
T6
Option byte
WDGHALT
bit in
0
1
x
T5
No Watchdog reset is generated. The MCU enters Halt mode.
The Watchdog counter is decremented once and then stops
counting and is no longer able to generate a watchdog reset until
the MCU receives an external interrupt or a reset.
If an external interrupt is received, the Watchdog restarts
counting after 256 or 4096 CPU clocks. If a reset is generated,
the Watchdog is disabled (reset state) unless Hardware
Watchdog is selected by option byte. For application
recommendations see
A reset is generated.
No reset is generated. The MCU enters Active-Halt mode. The
Watchdog counter is not decremented. It stop counting. When the
MCU receives an oscillator interrupt or external interrupt, the
Watchdog restarts counting immediately. When the MCU receives
a reset the Watchdog restarts counting after 256 or 4096 CPU
clocks.
Read/Write
T4
Description
Section 9.1.7
T3
T2
below.
On-chip peripherals
T1
T0
0
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