16t202da1j Pacer Components, 16t202da1j Datasheet - Page 15

• Manufacturer Part Number: 16t202da1j
• Description: 2x16 Lcd Compatible Vfd Module
• Manufacturer: Pacer Components

2X16 LCD Compatible VFD Module
6.2.7 Set CG-RAM Address
6.2.9 Read Busy Flag and Address
6.2.10 Write Data to CG or DD-RAM
6.2.8 Set DD-RAM Address
This instruction:
(1) Load a new 6-bit address into the address counter (ACC).
(2) Sets the address counter (ACC) to address CG-RAM.
Once "Set CG-RAM Address" has been executed, the contents of the address counter (ACC) will be automatically
modified after every access of CG-RAM, as determined by the "Entry Mode Set" instruction.
The active width of the address counter (ACC), when it is addressing CG-RAM, is 6 bits, so the counter will wrap
around to 3FH from 00H if more than 64 bytes of data are written into CG-RAM.
This instruction:
(1) Loads a new 7-bit address into the address counter (ACC).
(2) Sets the address counter (ACC) to point to the DD-RAM.
Once the "Set DD-RAM Address" instruction has been executed, the contents of the address counter (ACC) will be
automatically modified after each access of DD-RAM, as selected by the "Entry Mode Set" instruction
Read busy flag and address reads the busy flag (BF) indicating that the system is now internally operating on a
previously received instruction. If BF is 1, the internal operation is in progress.
The next instruction will not be accepted until BF is reset to 0. Check the BF status before the next write operation. At
the same time, the value of the address counter (ACC) in binary AAAAAAA is read out. This address counter (ACC) is
used by both CG-RAM and DD-RAM addresses, and its value is determined by the previous instruction. The address
contents are the same as the instructions setting the CG-RAM address and DD-RAM address.
This instruction writes 8-bit binary data (DB7 to DB0) into CG-RAM or DD-RAM. To write into CG-RAM or
DD-RAM is determined by the previous specification of the CG-RAM or DD-RAM address setting. After a write, the
address is automatically increased or decreased by 1 according to the entry mode. The entry mode also determines the
display shift. When data is written to the CG-RAM, the DB7, DB6 and DB5 bits are not displayed as characters.
*Valid DD-RAM Address Ranges
* BF = 1: busy state
* BF = 0: ready for next instruction, command receivable.
RS = 0, R/W = 0
RS = 0, R/W = 0
RS = 0, R/W = 1
RS = 1, R/W = 0
DB7
DB7
DB7
DB7
BF
0
1
2nd line
1st line
DB6
DB6
DB6
DB6
1
Number of Character
DB5
DB5
DB5
DB5
Character Code (Write-in)
DB4
DB4
DB4
DB4
40
40
ADD
ACC
DB3
DB3
DB3
DB3
ACG
16T202DA1J (Rev. 4.0)
DB2
DB2
DB2
DB2
Address Range
Page - 15 of 17
00H to 27H
40H to 67H
DB1
DB1
DB1
DB1
DB0
DB0
DB0
DB0
C0H ~ E7H for 2nd Line
80H ~ A7H for 1st Line
10H ~ FFH for CG-ROM Code
00H ~ 0FH for CG-RAM Code
Hex. Range
40H ~ 7FH
Hex. Range
Hex. Range
.