74f646a NXP Semiconductors, 74f646a Datasheet - Page 2

• Manufacturer Part Number: 74f646a
• Description: Octal Transceiver/register, Non-inverting/inverting 3-state
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FEATURES
ORDERING INFORMATION
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
NOTE: One (1.0) FAST unit load is defined as: 20 A in the HIGH state and 0.6 mA in the LOW state.
2003 Feb 04
Combines 74F245 and two 74F374 type functions in one chip
High impedance base inputs for reduced loading (70 A in HIGH
and LOW states)
Independent registers for A and B buses
Multiplexed real-time and stored data
Choice of non-inverting and inverting data paths
Controlled ramp outputs for 74F646A/74F648A
3-state outputs
300 mil wide 24-pin slim DIP package
Transceivers/registers
74F646A: Octal transceiver/register, non-inverting (3-State)
74F648A: Octal transceiver/register, inverting (3-State)
24-pin plastic slim DIP (300 mil)
A0 - A7, B0 - B7
A0-A7, B0-B7
CPAB
CPBA
PINS
SAB
SBA
24-pin plastic SOL
DIR
OE
DESCRIPTION
74F646A, 74F648A
TYPE
A and B inputs
A-to-B clock input
B-to-A clock input
A-to-B select input
B-to-A select input
Data flow directional control enable input
Output enable input
A, B outputs for N74F646A/N74F648A
DESCRIPTION
V
CC
= 5 V 10%, T
N74F646AN, N74F648AN
N74F646AD, N74F648AD
COMMERCIAL RANGE
TYPICAL f
2
185 MHz
ORDER CODE
transceiver circuits with 3-state outputs, D-type flip-flops, and control
DESCRIPTION
The 74F646A and 74F648A transceivers/registers consist of bus
circuitry arranged for multiplexed transmission of data directly from
the input bus or the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes HIGH.
Output enable (OE) and DIR pins are provided to control the
transceiver function. In the transceiver mode, data present at the
high impedance port may be stored in either the A or B register or
both.
The select pins (SAB, SBA) determine whether data is stored or
transferred through the device in real-time. The DIR determines
which bus will receive data when the OE is active LOW. In the
isolation mode (OE = HIGH), data from bus A may be stored in the
B register and/or data from bus B may be stored in the A register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of
the two buses, A or B may be driven at a time.
amb
max
= 0 C to +70 C
TYPICAL SUPPLY CURRENT (TOTAL)
HIGH/LOW
74F (U.L.)
1.0 / 0.033
1.0 / 0.033
1.0 / 0.033
1.0 / 0.033
1.0 / 0.033
1.0 / 0.033
3.5 / 0.116
750 / 80
74F646A/74F648A
105 mA
LOAD VALUE
15 mA / 48 mA
70 A / 70 A
20 A / 20 A
20 A / 20 A
20 A / 20 A
20 A / 20 A
20 A / 20 A
20 A / 20 A
HIGH / LOW
PKG DWG #
SOT222-1
SOT137-1
Product data