74f50109 NXP Semiconductors, 74f50109 Datasheet
74f50109
Available stocks
Related parts for 74f50109
74f50109 Summary of contents
Page 1
... Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics Product specification IC15 Data Handbook Philips Semiconductors INTEGRATED CIRCUITS 1990 Sep 14 ...
Page 2
... SOT109 Pin 16 CC GND = Pin 8 LOAD VALUE HIGH/LOW IEC/IEEE SYMBOL 20 A/250 A 20 A/250 15mA/20mA Product specification 74F50109 RD0 RD1 CP0 SD0 5 12 CP1 SD1 ...
Page 3
... The JK design allows operation flip–flop by tying J and K inputs together. The 74F50109 is designed so that the outputs can never display a metastable state due to setup and hold time violations. If setup time and hold time are violated the propagation delays may be extended beyond the specifications but the outputs will not glitch or display a metastable state ...
Page 4
... Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive Figure 2. 74F74 Q output triggered by Q output, Setup and Hold times violated Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive Figure 3. 74F74 Q output triggered by Q output, Setup and Hold times violated September 14, 1990 4 Product specification 74F50109 SF00602 SF00588 ...
Page 5
... X = Don’t care = Low–to–high clock transition Load ”1” (set) = Not low–to–high clock transition Load ”0” (reset Both outputs will be high if both SD and RD go low simultaneously Hold ’no change” 5 Product specification 74F50109 SF00589 ...
Page 6
... MAX 0. MAX 0. MAX MAX CC , the use of high-speed test apparatus and/or sample-and-hold OS 6 Product specification 74F50109 RATING UNIT –0.5 to +7.0 V –0.5 to +7.0 V – –0 +70 C –65 to +150 C LIMITS UNIT NOM MAX 5 ...
Page 7
... CC LIMITS T = +25 C amb TEST V = +5.0V CC CONDITION C = 50pF 500 L MIN TYP MAX 1.5 Waveform 1 1.5 1.0 Waveform 1 1.0 3.0 Waveform 1 4.0 Waveform 2 3.5 Waveform 3 3.0 7 Product specification 74F50109 +70 C amb V = +5.0V 10% UNIT 50pF 500 L MIN MAX 90 ns 2.0 6.5 ns 2.0 6.5 3.0 8.5 ns 3.0 8.5 1 +70 C amb ...
Page 8
... V M Waveform 4. Output skew SF00603 90% NEGATIVE V M PULSE 10 TLH ( 90% POSITIVE V PULSE M 10% INPUT PULSE REQUIREMENTS family amplitude of OUT 74F 3.0V 8 Product specification 74F50109 PHL PLH SF00050 sk( SF00590 t AMP (V) ...
Page 9
... Philips Semiconductors Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics DIP16: plastic dual in-line package; 16 leads (300 mil) 1990 Sep 14 9 Product specification 74F50109 SOT38-4 ...
Page 10
... Philips Semiconductors Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics SO16: plastic small outline package; 16 leads; body width 3.9 mm 1990 Sep 14 10 Product specification 74F50109 SOT109-1 ...
Page 11
... Philips Semiconductors Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics 1990 Sep 14 NOTES 11 Product specification 74F50109 ...
Page 12
... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors yyyy mmm dd [1] Copyright Philips Electronics North America Corporation 1998 print code Document order number: 12 Product specification 74F50109 All rights reserved. Printed in U.S.A. Date of release: 10-98 9397-750-05214 ...