sm5170 Nippon Precision Circuits Inc, (NPC), sm5170 Datasheet - Page 5

• Manufacturer Part Number: sm5170
• Description: Pll Synthesizer Ic
• Manufacturer: Nippon Precision Circuits Inc, (NPC)

FUNCTIONAL DESCRIPTION
Frequency Divider Data
The input data should be specified keeping in mind the V
LE pins into the shift register and latch which operate from the V
is not needed and can be ON or OFF.
The control data input uses a 3-line 24-bit serial interface comprising the clock (CLK), data input (DATA) and
latch enable (LE). The data is input with the MSB first. The last two bits (23rd + 24th) are used as the latch
select control bits. Data is written to the shift register on the rising edge of the clock signal. Accordingly, the
data should change state on the falling edge of the clock signal. Data is transferred from the shift register to the
latch when the latch enable (LE) signal goes HIGH. Accordingly, the latch enable signal should be held LOW
while data is being written to the shift register.
The clock and data input signals are both ignored when the latch enable signal goes HIGH. Also, the CLK,
DATA and LE inputs should be tied LOW when not setting data.
Input Data Description
Latch select
The last two data bits determine the status of the shift register data latch.
Bit 23
0
0
DATA
DATA
CLK
LE
Bit 24
MSB
MSB
0
1
1
1
2
2
Swallow counter and main counter frequency divider ratio latch select
Reference frequency counter divider ratio data and LD output latch select
3
3
4
4
5
5
6
6
Figure 1. Frequency divider data format
7
7
Figure 2. Latch select data format
8
8
9
9
Latch
10
10
SM5170AV
11
11
12
12
DD2
13
13
supply. The data is input using CLK, DATA and
14
14
DD2
15
15
supply. The V
16
16
17
17
18
18
SEIKO NPC CORPORATION —5
19
19
DD1
Control bits
20
Control bits
20
supply level, however,
21
21
22
22
23
23
LSB
24
LSB
24