sm5170 Nippon Precision Circuits Inc, (NPC), sm5170 Datasheet - Page 6

• Manufacturer Part Number: sm5170
• Description: Pll Synthesizer Ic
• Manufacturer: Nippon Precision Circuits Inc, (NPC)

FIN input frequency Divider (N-counter) Structure
The FIN input frequency divider generates a comparator frequency signal (FV), which is input to the phase
comparator, by dividing the VCO signal input on pin FIN. The phase comparator is comprised of dual modulus
prescalers, a 5-bit swallow counter and a 12-bit main counter.
Frequency settings
Counter set ranges
FIN input frequency divider ratio range
Swallow counter and main counter data
The swallow counter and main counter which determine the FIN input frequency divider ratio are set by bits 1
to 12 and bits 13 to 17, respectively. The voltage signal output on pin DB is set by bits 18 to 22.
FIN input frequency divider example
If the VCO output is (f
comparator frequency (f
Therefore, the swallow counter count is 4 (00100)
(000100111010)
DB fast-lockup data
The output voltage on pin DB provides an additional boost to charge the external lowpass filter capacitor for
faster lockup times. One of 31 possible output voltage level signals is selected by bits 18 to 22.
The DB level signal output occurs during 2 clock cycles when the reference frequency divider comparator sig-
nal FR is generated after OPR goes HIGH, or after LE goes LOW when data is written. The DB output subse-
quently becomes high impedance.
Note that if bits 18 to 22 are all set to 0, this function is not activated and DB remains in the high impedance
state.
Input data format example
FIN input frequency divider = 10052, DB is high impedance:
MSB
MSB
1
2
0
1
2
11
11
2
Figure 4. Swallow counter and main counter frequency divider data example
Figure 3. Swallow counter and main counter frequency divider data format
.
2
2
0
2
2
10
10
3
2
3
2
0
Prescaler
Swallow counter
Main counter
FIN input frequency divider ratio
Prescaler
Swallow counter
Main counter
9
9
VCO
R
4
2
1
4
2
)) is 25kHz, then the FIN input frequency divider ratio N is given by:
N =
(12bit : 32 to 4095)
8
8
(12bit : 32 to 4095)
), the output frequency (f
Main Counter
5
2
0
5
2
Main Counter
7
7
f
f
6
2
CH
6
2
0
LO
6
6
7
2
7
2
1
5
=
5
8
2
8
2
1
4
4
f
VCO
f
N
9
2
1
9
2
Control bits
Control bits
3
3
10
10
2
2
0
=
2
2
11
11
2
1
2
(251.3)
(0.025)
SM5170AV
1
1
12
12
2
0
2
LO
2
0
0
DBpin Condition Select bits
DBpin Condition Select bits
and the main frequency divider counter count is 314
) is 251.3MHz, and the channel bandwidth (f
13
13
2
0
2
Swallow Counter
Swallow Counter
4
4
(5bit : 0 to 31)
(5bit : 0 to 31)
= 10052 = 32 314 + 4
14
14
2
2
0
3
3
P and P + 1
S
M
N = (P + 1) × S + P × (M − S)
N
P = 32, P + 1 = 33
S = 0 to 31
M = 32 to 4095
N = 1056 to 131071
15
15
2
2
1
= P × M + S (where M > S)
2
2
16
16
2
0
2
1
1
17
17
2
2
0
0
0
18
18
2
2
0
4
4
19
19
2
0
2
3
3
20
20
2
0
2
2
2
SEIKO NPC CORPORATION —6
21
21
2
0
2
1
1
22
22
2
0
2
0
0
23
23
0
LSB
LSB
24
24
0
CH
: Phase