sm59128 SyncMOS Technologies,Inc, sm59128 Datasheet - Page 21

• Manufacturer Part Number: sm59128
• Description: 8-bits Micro-controller Embedded 128kb Flash & 1kb Ram & Iic & Spwm
• Manufacturer: SyncMOS Technologies,Inc

MASTER: If set the MASTER bit, the module will generate a start condition to the SDA and SCL lines and send out the
TXAK: The bit (TXAK) control the acknowledge transmit in RECEIVE mode, if it is cleared, a low (Ack) will be
IIC Address Register (IICA, $C1)
IICA[7:1] : These 7 bits can be the chip address in slave mode or the calling address when in master mode. This
EXTADDR : The EXTAD bit is set to expand the chip address of this module. When it is one, the module will
IIC Control Register (IICC1, $C2)
IICE: If this IIC module Enable bit (IE1) is set, the IIC module is enable. If the IE1 is clear, the interface is disable and all
BB : The Bus Busy Flag is set after a start condition is detected, and is reset when a stop condition is detected. Reset
IICFS[2:0] :The three Baud Rate select bits will select one of the eight clock rates as the master clock when the module
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M027Ver: B SM59128
Reset value:
Reset value:
Read:
Read:
Write:
Write:
calling address which is stored in the IADR register. But if the TFIF flag is set when transmit fail occurs on the
lines, the module will discard the master mode by clearing the MASTER bit and release both SDA and SCL
lines immediately. This bit can also be cleared by writing zero to it or when the NAKIF is set. When the
MASTER bit is cleared either by set NAKIF or software the module will generate a stop condition to the lines
after the current byte transmission is done, and IGNORE the IICTDB data when next IIC transmit cycle if this
data had not been transmit out. Reset clears this bit.
generated at the 9th clock after receiving 8 bits data. When TXAK is set, a high (NoAck) will be generated at the
9th clock after receiving 8 bits data. Reset clears this bit.
SyncMOS Technologies International, Inc.
register is set as $A0 upon reset.
acknowledge the general call address $00 and the address comparison circuit will only compare the 4
MSB bits in the LADR register. When it is zero, the module will only acknowledge to the specific address
which is stored in the IADR register. It is zero after reset.
is in master mode. The serial clock frequency is equal to the external clock divided by the certain divider.
These bits are cleared upon reset.
clears this bit.
flags will restore its reset default states. Reset to clear this bit.
IICA.7
bit-7
bit-7
IICE
1
0
IICA.6
0
0
-
IICA.5
1
0
-
IICA.4
21
Embedded 128KB flash & 1KB RAM & IIC & SPWM
0
0
-
IICA.3
BB
0
0
IICFS2
IICA.2
0
0
8-Bits Micro-controller
IICFS1
IICA.1
0
0
EXTADDR
SM59128
IICFS0
06/2009
bit-0
bit-0
0
1