sm59128 SyncMOS Technologies,Inc, sm59128 Datasheet - Page 23

• Manufacturer Part Number: sm59128
• Description: 8-bits Micro-controller Embedded 128kb Flash & 1kb Ram & Iic & Spwm
• Manufacturer: SyncMOS Technologies,Inc

Reset value:
Reset value:
IIC Transmit Data Buffer (IICTxD, $C4)
The data written into this register will be automatically downloaded to the shift register when the module detects a
calling address is matched and the bit 0 of the received data is one (Slave transmit mode) or when the data in the shift
register has been transmitted with received acknowledge bit (RXAK) =0 in transmit mode. So if the program doesn’t
write the data into the IICTDB register before the matched calling address is detected or the shift register has been
transmitted out, the module will pull down the SCL line (after receive acknowledge bit). If write a data to the
register, then the written data will be downloaded to the shift register immediately and the module will release the SCL
line, and the TXIF flag is set to generate another interrupt request for next data. So the S/W may need to write the next
data to the
transmitted over again with RXAK=0. If the module receiver non-acknowledge (RXAK=1), the module will release the
SDA line for master to generate Stop or Repeated Start conditions.
IIC Receive Data Buffer (IICRxD, $C5)
The IIC Receive Data Buffer (IICRxD) contains the last received data when the MATCH flag is one or the calling
address from master when the MATCH flag is zero. The IICRxD register will be updated after a data byte is received
and the previous received data had been read out, otherwise the DDC module will pull down to SCL line to inhabit the
next data transfer. It is a read-only register. The read operation of this register will clear the RXIF flag. After the RXIF
flag is cleared, the register can load the received data again and set the RXIF flag the venerate interrupt request for
reading the newly received data.
7.2 IIC Interrupt
The IIC module will generate IIC interrupt while hardware circuit detects START signal of IICSDA and IICSCL. The IIC
interrupt vector locates at $3B. There are three SFRs for configuring IIC interrupt: IP1, IE1 and IFR. To use IIC interrupt
is the same as to use other generic 8052 interrupts. That means using EIIC of IE1 for enable/disable IIC interrupt,
using PIIC for assign IIC interrupt priority. Whenever IIC interrupt occurs, IICIF will be set to 1. After IIC interrupt
subroutine (vector) been executed, IICIF will be cleared to 0.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M027Ver: B SM59128
Read:
Write:
Read:
Write:
SyncMOS Technologies International, Inc.
IICTxD
IICTx
Bit-7
IICRD.7
D.7
0
Bit-7
0
register and for the auto downloading of data to the shift register after the data in the shift register is
IICTxD.6
0
IICRD.6
0
IICTxD.5
IICRD.5
0
0
IICTxD.4
IICRD.4
0
0
23
Embedded 128KB flash & 1KB RAM & IIC & SPWM
IICTxD.3
IICRD.3
0
0
IICTxD.2
IICRD.2
0
0
8-Bits Micro-controller
IICRD.1
IICTxD.1
0
0
SM59128
06/2009
IICRD.0
IICTxD.0
bit-0
0
bit-0
IICTxD
0