sm59d03g2c25 SyncMOS Technologies,Inc, sm59d03g2c25 Datasheet - Page 31

• Manufacturer Part Number: sm59d03g2c25
• Description: 8-bits Micro-controller 8kb+ Isp Flash & 1kb Ram Embedded
• Manufacturer: SyncMOS Technologies,Inc

Mnemonic
WDTC
WDTK
8
The watchdog timer is an 8-bit counter that is incremented once every WDTCLK clock cycle. After
an external reset, the watchdog timer is disabled and all registers are set to zero.
When SM59D03G2 is reset, it will read internal setting for the bit WDTEN.When the WDTEN is
selected ,the watchdog function will enable. The WDTM[2:0] is control WDTCLK. User can select
WDTEN on the writer.
The watchdog timer will reset the system after 256 WDTCLK is reached. Once the watchdog is
started it cannot be stopped. To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC.
After WDTE set to 1, the 16-bit counter starts to count. It will generate a reset signal when
overflows. The WDTE bit will be cleared to 0 automatically when SM59D04G2 been reset, either
hardware reset or WDT reset
To reset the WDT is done by setting 1 to the CLEAR bit of WDTC before the counter overflow. This
will clear the content of the 16-bit counter and let the counter re-start to count from the beginning.
The SFR WDTK[7:0] must be set first. The first value set to it is 1Eh, then the next value is E1h.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M030
OverFlow Period 1.58ms
WDTM[2:0]
Watchdog timer
WDTM[2:0]:
WDTE:
CLEAR
Description
Watchdog timer
control register
Watchdog timer
refresh key
Mnemonic: WDTC
WDTE
7
000
6
-
Direct
8Eh
8Fh
Table 8-1 Watchdog Timer Overflow Period：
3.15ms
Watchdog timer over flow period setting.
Watchdog timer Enable.
WDTE=0：Disable WDT function either the WDTEN was setting on
the Writer。
WDTE=1：Enable WDT function when the WDTEN was setting on
the Writer。
This bit will be cleared to 0 automatically when MCU been reset,
either hardware reset or WDT reset。
Setting this bit the Watchdog timer counter clear and re-start to count
from the Beginning。
001
CLEAR
WDTE
5
Bit 7
6.30ms
010
4
-
Bit 6
Watchdog Timer
-
12.60ms
011
31
CLEAR
3
-
Bit 5
WDTM2
25.12ms
Bit 4
2
100
WDTK[7:0]
-
WDTM1
8KB+ ISP Flash & 1KB RAM embedded
Bit 3
1
50.41ms 100.82ms 201.65ms
-
101
Address: 8Eh
WDTM0
WDTM2
Ver.C SM59D03G2 07/2009
Bit 2
0
8-Bits Micro-controller
110
Reset
00H
WDTM1
Bit 1
SM59D03G2
111
WDTM0
Bit 0
RESET
00H
00H