sm59264 SyncMOS Technologies,Inc, sm59264 Datasheet - Page 23

• Manufacturer Part Number: sm59264
• Description: 8-bits Micro-controller With 128kb Flash & 1kb Ram & Twsi & Spwm Embedded
• Manufacturer: SyncMOS Technologies,Inc

MASTER: If set the MASTER bit, the module will generate a start condition to the SDA and SCL lines and send out the
NAKIF: The NonAcknowledge Interrupt Flag is only set in the master transmit mode when there is no acknowledge bi
RXAK: If the received acknowledge bit (RXAK) is low, it indicates an acknowledge signal has been received after the
speed can be selected to 6.25K~400Kbps by software setting the BR[2..0] contrtol bit. The TWSI module provided 4
interrupts (Rx, Tx, NonAck, TxFail). It will generate and/or detects START, repeated START and STOP signals
automatically in master mode. The maximum communication length and the number of devices that can be connected
are limited by a maximum bus capacitance of 400pF.
7.1 TWSI Registers
TWSI Status Register (TWSIS, $C0)
Note1:Read and Writer’0’ only
Note2:Read only
Note3:Read and Writer
RXIF: The data Receive Interrupt Flag (RXIF) is set after the TWSIRDB (TWSI Receive Data Buffer) is loaded with a
TXIF: The data Transmit Interrupt Flag is set when the data of the TWSITDB register is downloaded to the shift register
TFIF: The Transmit Fail Interrupt Flag is set when the data transmit is fail, which as set MASTER bit when the BB has
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M012 Ver B SM59264
The TWSI module uses the SCL (clock) and the SDA (data) line to communicate with external TWSI interface. Its
Read / Write:
Reset value:
or Master Transmit mode the IADR is downloaded to the shift register. It is software’s responsibility to fill the
TWSITDB register with new data when this bit is set. This bit is cleared by writing zero to it, write data to
TWSITDB or when reset.
been set by detecting the start condition on the lines or when the module is transmitting a One to SDA line but
detected a Zero from SDA line in master mode, which is also called arbitration loss. This bit is cleared by writing
Zero to it or by reset.
completion of 8 data bits transmission on the bus. If RXAK is high, it indicates no acknowledge signal has been
detected at the 9th clock. Then the module will release the SDA line for the master to generate Stop or Repeated
Start condition. It is set upon reset.
newly receive data. Once the IRDB is loaded with received data, no more received data can be loaded to the
TWSIRDB register again.
detected after one byte data or calling address is transferred. This bit is cleared by writing Zero to it or by reset.
calling address which is stored in the IADR register. But if the TFIF flag is set when transmit fail occurs on the
SyncMOS Technologies International, Inc.
Note1
RXIF
bit-7
0
Note1
TXIF
0
Note1
TFIF
0
with 128KB flash & 1KB RAM & TWSI & SPWM embedded
NAKIF
Note1
23
0
Unused
-
RXAK
Note2
1
MASTER
8-Bits Micro-controller
Note3
0
SM59264
TXAK
Note3
bit-0
05/2009
0