sm59264 SyncMOS Technologies,Inc, sm59264 Datasheet - Page 24

• Manufacturer Part Number: sm59264
• Description: 8-bits Micro-controller With 128kb Flash & 1kb Ram & Twsi & Spwm Embedded
• Manufacturer: SyncMOS Technologies,Inc

TXAK: The bit (TXAK) control the acknowledge transmit in RECEIVE mode, if it is cleared, a low (Ack) will be
TWSI Address Register (TWSIA, $C1)
TWSIA[7:1] : These 7 bits can be the chip address in slave mode or the calling address when in master mode. This
EXTADDR : The EXTAD bit is set to expand the chip address of this module. When it is one, the module will
TWSI Control Register (TWSIC1, $C2)
TWSIE: If this TWSI module Enable bit (IE1) is set, the TWSI module is enable. If the IE1 is clear, the interface is
BB : The Bus Busy Flag is set after a start condition is detected, and is reset when a stop condition is detected. Reset
TWSIFS[2:0] :The three Baud Rate select bits will select one of the eight clock rates as the master clock when the
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M012 Ver B SM59264
lines, the module will discard the master mode by clearing the MASTER bit and release both SDA and SCL lines
Reset value:
Reset value:
Read:
Read:
Write:
Write:
immediately. This bit can also be cleared by writing zero to it or when the NAKIF is set. When the MASTER bit
is cleared either by set NAKIF or software the module will generate a stop condition to the lines after the current
byte transmission is done, and IGNORE the TWSITDB data when next TWSI transmit cycle if this data had not
been transmit out. Reset clears this bit.
generated at the 9th clock after receiving 8 bits data. When TXAK is set, a high (NoAck) will be generated at the
9th clock after receiving 8 bits data. Reset clears this bit.
SyncMOS Technologies International, Inc.
register is set as $A0 upon reset.
acknowledge the general call address $00 and the address comparison circuit will only compare the 4
MSB bits in the LADR register. When it is zero, the module will only acknowledge to the specific address
which is stored in the IADR register. It is zero after reset.
module is in master mode. The serial clock frequency is equal to the external clock divided by the
certain divider. These bits are cleared upon reset.
clears this bit.
disable and all flags will restore its reset default states. Reset clears this bit.
TWSIA.7
TWSIE
bit-7
bit-7
1
0
TWSIA.6
TWSIFS[2:0]
0
0
-
TWSIA.5
1
0
-
with 128KB flash & 1KB RAM & TWSI & SPWM embedded
TWSIA.4
24
0
0
-
TWSIA.3
Baud Rate
BB
0
0
TWSIFS2
TWSIA.2
0
0
TWSIFS1
TWSIA.1
8-Bits Micro-controller
0
0
EXTADDR
SM59264
TWSIFS0
bit-0
05/2009
bit-0
0
1