fm3316 Ramtron Corporation, fm3316 Datasheet - Page 17

• Manufacturer Part Number: fm3316
• Description: 3v Integrated Processor Companion With Memory
• Manufacturer: Ramtron Corporation

Rev. 1.1
Dec. 2007
02h
01h
CALS
CAL.4-0
00h
/OSCEN
AF
CF
AEN
CAL
W
R
Reserved
Timekeeping – Seconds
Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble
contains the upper digit and operates from 0 to 5. The range for the register is 0-59. Battery-backed, read/write.
CAL/Control
Calibration Sign: Determines if the calibration adjustment is applied as an addition to or as a subtraction from the
time-base. This bit can be written only when CAL=1. Nonvolatile, read/write.
Calibration Code: These five bits control the calibration of the clock. These bits can be written only when
CAL=1. Nonvolatile, read/write.
RTC/Alarm Control
Oscillator Enable. When set to ‘1’, the oscillator is halted. When set to ‘0’, the oscillator runs. Disabling the
oscillator can save battery power during storage. On a power-up without a V
V
read/write.
Alarm Flag: This bit is set to 1 when the time and date match the values stored in the alarm registers with the
Match bit(s) = 0. The user must clear it to ‘0’. Battery-backed. (internally set, user must clear bit)
Century Overflow Flag: This bit is set to a 1 when the values in the years register overflows from 99 to 00. This
indicates a new century, such as going from 1999 to 2000 or 2099 to 2100. The user should record the new
century information as needed. The user must clear the CF bit to ‘0’. Battery-backed. (internally set, user must
clear bit)
Alarm Enable: This bit enables the alarm function. When AEN is set (and CAL cleared), the ACS pin operates as
an active-low alarm. The state of the ACS pin is detailed in Table 2. When AEN is cleared, no new alarm events
that set the AF bit will be generated. Clearing the AEN bit does not automatically clear AF. Battery-backed.
Calibration Mode: When CAL is set to 1, the clock enters calibration mode. When CAL is set to 0, the clock
operates normally, and the ACS pin is controlled by the RTC alarm. Battery-backed, read/write.
Write Time. Setting the W bit to 1 freezes updates of the user timekeeping registers. The user can then write
them with updated values. Setting the W bit to 0 causes the contents of the time registers to be transferred to the
timekeeping counters. Battery-backed, read/write.
Read Time. Setting the R bit to ‘1’ copies a static image of the timekeeping core and places it into the user
registers. The user can then read them without concerns over changing values causing system errors. The R bit
going from 0 to 1 causes the timekeeping capture, so the bit must be returned to 0 prior to reading again. Battery-
backed, read/write.
Reserved bits. Do not use. Should remain set to 0.
BAK
OSCEN
D7
0
D7
D7
-
source has been applied, this bit is internally set to ‘1’, which turns off the oscillator. Battery-backed,
10 sec.2
D6
D6
D6
AF
-
10 sec.1
D5
CALS
D5
D5
CF
10 sec.0
D4
CAL.4
AEN
D4
D4
Seconds.3
FM33256/FM3316 SPI Companion w/ FRAM
Reserved
CAL.3
D3
D3
D3
Seconds.2
CAL.2
CAL
D2
D2
BAK
D2
source or on a power-up after a
Seconds.1
CAL.1
D1
D1
W
D1
Page 17 of 28
Seconds.0
CAL.0
D0
D0
D0
R