isl55210 Intersil Corporation, isl55210 Datasheet - Page 14

• Manufacturer Part Number: isl55210
• Description: Wideband, Low-power, Ultra-high Dynamic Range Differential Amplifier
• Manufacturer: Intersil Corporation

The maximum internal junction temperatures would occur at
maximum supply voltage, +85°C maximum ambient operating,
and where the QFN exposed pad is not tied to a conductive layer.
Where the QFN must be mounted with an insulating layer to the
exposed metal plate, such as in a split supply application, device
measurements show an increased thermal impedance junction
to ambient of +120°C/W. Using this, and a maximum quiescent
internal power on 4.5V absolute maximum, which shows 45mA
for +85°C maximum operating ambient from Figure 27, we get
4.5V * 45mA * +120°C/W = +24°C rise above +85°C or
approximately +109°C operating T
the specified Absolute Maximum operating junction temperature
of +135°C.
Noise Analysis
The decompensated voltage feedback design of the ISL55210
provides very low input voltage and current noise. While a
detailed noise model using arbitrary external resistors can be
made, most applications will have a balanced feedback network
with the two R
resistors equal. Figure 33 shows the test circuit used to measure
the output noise with the noise terms detailed. The aim here was
to measure the output noise with two different resistor settings
to extract out a model for the input referred En and In terms for
just the amplifier itself.
With equal feedback and gain resistors, the total output noise
expression becomes very simple. This is:
e
The NG term in Equation 1 is the Noise Gain = 1 + R
last term in Equation 1 captures both the R
noise terms. If we assume a 50Ω source in Test Circuit #1, the
total R
through the transformer to look like a 50Ω source on each side.
This gives a lower noise gain (3V/V) than signal gain (4V/V) for
just the amplifier. The total gain in Test Circuit #1 is still
approximately 1.4 * 4 = 5.6V/V including the transformer step
up.
1µF
1µF
0
=
G
(
4kTR
e
4kTR
resistor value will be 100Ω as that 50Ω will come
n
*
*
•
g
FIGURE 33. NOISE MODEL AND TEST CIRCUIT
g
NG
R
R
F
G
G
)
2
(feedback) resistors equal and the two R
i
i
n
n
+
*
*
2
(
+
i
-
n
4kTR
4kTR
R
*
*
f
*
)
f
e
2
f
n
+
R
R
F
F
2 4kTR
ISL55210
14
(
J
maximum - still well below
f
NG
)
e
O
25
25
F
and R
ADT1-1WT
G
F
resistor
1:1
/R
G
G
. The
ISL55210
1µF
(gain)
(EQ. 1)
50
Putting in NG = 3, R
noise terms of En = 0.85nV/√Hz and In = 5pA/√Hz into Equation 1
(4kT = 1.6E - 20J) gives a total output differential noise
voltage = 5.26nV/√Hz. Input referring this to the input side of the
transformer of Test Circuit #1 gives an input referred spot noise
of only 0.88nV/√Hz. This extremely low input referred noise is a
combination of low amplifier noise terms and the effect of the
input transformer configuration.
Driving Cap and Filter Loads
Most applications will drive a resistive or filter load. The
ISL55210 is robust to direct capacitive load on the outputs up to
approximately 10pF. For frequency response flatness, it is best to
avoid any output pin capacitance as much as possible - as that
capacitance increases, the high frequency portion of the
ISL55210 (>1GHz) response will start to show considerable
peaking. No oscillations were observed up through 10pF load on
each output.
For AC coupled applications, an output network that is a small
series resistor (10Ω to 50Ω) into a blocking cap is preferred. This
series resistor will isolate parasitic capacitance to ground from
the internally closed loop output stage of the amplifier and
de-queue the self resonance of the blocking capacitors. Once the
output stage sees this resistive element first, the remaining part
of the filter design can be done without fear of amplifier
instability.
Driving ADCs
Many of the intended applications for the ISL55210 are as a low
power, very high dynamic range, last stage interface to high
performance ADCs. The lowest power ADCs, such as the
ISLA112P50 shown on the front page, include an innovative
"Femto-Charge" internal architecture that eliminates op amps
from the ADC design and only passes signal charge from stage to
stage. This greatly reduces the required quiescent power for
these ADCs but then that signal charge has to be provided by the
external circuit at the two input pins. This appears on an ADC like
the
current that must be supplied by the interface circuit. At
500MHz, this DC current is 1.3mA on each input for the
ISLA112P50.
Most interfaces will also include an interstage noise power
bandlimiting filter between the amplifier and the ADC. This filter
needs to be designed considering the loading of the amplifier,
any V
and this I
topologies suitable for different situations.
1. AC coupled, broadband RLC interstage filter design. This
ISLA112P50
approach lets the amplifier operate at its desired output
common mode, then provides the ADC common mode
voltage and current through a bias path as part of the filter
design’s last stage R values. The V
loss from that voltage to the ADC inputs due to the I
current. This circuit is the one shown on the front page where
we get a usable frequency range from about 500kHz to
150MHz.
CM
level shifting that needs to take place, the filter shape,
CM
issue into the ADC input pins. Here are 4 example
as a clock rate dependent common mode input
F
= 200Ω, R
G
= 100Ω with the ISL55210
B
is set to include the IR
March 2, 2011
CM
FN7811.0