isl23348 Intersil Corporation, isl23348 Datasheet

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isl23348

Manufacturer Part Number
isl23348
Description
Quad, 128 Tap, Low Voltage Digitally Controlled Potentiometer Xdcp™
Manufacturer
Intersil Corporation
Datasheet

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Quad, 128 Tap, Low Voltage Digitally Controlled
Potentiometer (XDCP™)
ISL23348
The ISL23348 is a volatile, low voltage, low noise, low power,
128 tap, quad digitally controlled potentiometer (DCP) with an
I
switches and control logic on a monolithic CMOS integrated
circuit.
Each digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I
volatile Wiper Register (WRi, i = 0, 1, 2, 3) that can be directly
written to and read by the user. The contents of the WRi
controls the position of the wiper. When powered on, the wiper
of each DCP will always commence at mid-scale (64 tap
position).
The low voltage, low power consumption, and small package
of the ISL23348 make it an ideal choice for use in battery
operated equipment. In addition, the ISL23348 has a V
pin allowing down to 1.2V bus operation, independent from the
V
directly to the ISL23348 without passing through a voltage
level shifter.
The DCP can be used as a three-terminal potentiometer or as a
two-terminal variable resistor in a wide variety of applications
including control, parameter adjustments, and signal processing.
Applications
• Power supply margining
• Trimming sensor circuits
• Gain adjustment in battery powered instruments
• RF power amplifier bias compensation
2
2
August 24, 2011
FN7903.1
CC
C Bus™ interface. It integrates four DCP cores, wiper
C bus interface. Each potentiometer has an associated
10000
FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP
value. This allows for low logic levels to be connected
8000
6000
4000
2000
0
0
POSITION, 10kΩ DCP
32
TAP POSITION (DECIMAL)
1
64
96
LOGIC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
1-888-INTERSIL or 1-888-468-3774
128
Features
• Four potentiometers per package
• 128 resistor taps
• 10kΩ, 50kΩ or 100kΩ total resistance
• I
• Maximum supply current without serial bus activity
• Shutdown mode
• Power supply
• Wiper resistance: 70Ω typical @ V
• Power-on preset to mid-scale (64 tap position)
• Extended industrial temperature range: -40
• 20 Ld TSSOP or 20 QFN packages
• Pb-free (RoHS compliant)
- No additional level translator for low bus supply
- Three address pins allow up to eight devices per bus
(standby)
- 5µA @ V
- 2µA @ V
- Forces the DCP into an end-to-end open circuit and RWi is
- Reduces power consumption by disconnecting the DCP
- V
- V
2
ISL23348
C serial interface
1 DCP
connected to RLi internally
resistor from the circuit
All other trademarks mentioned are the property of their respective owners
OF
CC
LOGIC
= 1.7V to 5.5V analog power supply
= 1.2V to 5.5V I
V
CC
CC
REF
RH1
RL1
FIGURE 2. V
and V
and V
|
Copyright Intersil Americas Inc. 2011. All Rights Reserved
RW1
LOGIC
LOGIC
2
= 5V
= 1.7V
REF
C bus/logic power supply
+
-
ADJUSTMENT
ISL28114
CC
= 3.3V
°
C to +125
V
REF_M
°
C

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isl23348 Summary of contents

Page 1

... DCP will always commence at mid-scale (64 tap position). The low voltage, low power consumption, and small package of the ISL23348 make it an ideal choice for use in battery operated equipment. In addition, the ISL23348 has a V pin allowing down to 1.2V bus operation, independent from the V value ...

Page 2

... LOGIC 10 A0 ISL23348 (20 LD QFN) TOP VIEW RH0 2 3 RL1 4 RW1 5 RH1 6 GND ISL23348 V CC POWER UP INTERFACE LEVEL CONTROL SHIFTER AND STATUS LOGIC GND Pin Descriptions TSSOP RL3 3 19 RW3 18 RH3 4 17 RL2 16 RW2 5 15 ...

Page 3

... RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL23348. For more information on MSL please see techbrief TB363. 3 ...

Page 4

... Resistor Noise Density Feed Thru Digital Feed-through from Bus to Wiper Wiper at middle point PSRR Power Supply Reject Ratio 4 ISL23348 Thermal Information Thermal Resistance (Typical TSSOP Package (Notes QFN Package (Notes Maximum Junction Temperature (Plastic Package .+150°C Storage Temperature Range .-65° ...

Page 5

... RHEOSTAT MODE (Measurements between RW and RL pins with RH not connected, or between RW and RH with RL not connected) R Integral Non-linearity, Guaranteed INL (Note 18) Monotonic R Differential Non-linearity, Guaranteed DNL (Note 17) Monotonic 5 ISL23348 = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. LOGIC (Continued) TEST CONDITIONS W option U, T option W option U, T option W option U, T option W option ...

Page 6

... I V Shutdown Current LOGIC LOGIC SHDN I V Shutdown Current CC SHDN CC I Leakage Current, at Pins A0, A1, A2, LkgDig SDA, SCL 6 ISL23348 = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. LOGIC (Continued) TEST CONDITIONS W option 2. option 1. option 2. option 1.7V CC ...

Page 7

... START Condition Hold Time HD:STA t Input Data Set-up Time SU:DAT t Input Data Hold Time HD:DAT 7 ISL23348 V = 2.7V to 5.5V 1.2V to 5.5V over recommended operating conditions unless otherwise stated. CC LOGIC (Continued) TEST CONDITIONS W option; SCL rising edge at the acknowledge bit after data byte to wiper new position from 10% to 90% of the final value. U option ...

Page 8

... CC 22. VMATCH = [V(RWx)i - V(RWy)i]/LSB, for 127 and 23. RMATCH = (RWi,x - RWi,y)/MI, for 127 and ISL23348 For SCL, SDA, A0, A1, A2 unless otherwise noted. TEST CONDITIONS From SCL rising edge crossing 70 SDA rising edge crossing 30 From SDA rising edge to SCL falling edge ...

Page 9

... DCP Macro Model Timing Diagrams SDA vs SCL Timing SCL t SU:STA t HD:STA SDA (INPUT TIMING) SDA (OUTPUT TIMING) A0, A1 and A2 Pin Timing START SCL SDA A0, A1 ISL23348 R TOTAL 32pF 32pF 32pF HIGH LOW t SU:DAT t HD:DAT CLK 1 ...

Page 10

... TAP POSITION (DECIMAL) FIGURE 5. 10kΩ INL vs TAP POSITION, V 0.15 0.10 0.05 0.00 -0.05 -0.10 -0. TAP POSITION (DECIMAL) FIGURE 7. 10kΩ RDNL vs TAP POSITION ISL23348 0.04 0.02 0.00 -0.02 -0.04 96 128 0   = 3.3V, +25°C FIGURE 4. 50kΩ DNL vs TAP POSITION 0.16 0.12 0.08 0.04 0.00 96 128 0   = 3.3V, +25°C FIGURE 6. 50kΩ INL vs TAP POSITION ...

Page 11

... TAP POSITION (DECIMAL) FIGURE 11. 10kΩ WIPER RESISTANCE vs TAP POSITION, V 200 150 100 TAP POSITION (DECIMAL) FIGURE 13. 10kΩ TCv vs TAP POSITION ISL23348 (Continued) 0.08 0.04 0.00 -0.04 -0.08 96 128 0   = 3.3V, +25°C FIGURE 10. 50kΩ RINL vs TAP POSITION 120 +125°C ...

Page 12

... FIGURE 15. 10kΩ TCr vs TAP POSITION TAP POSITION (DECIMAL) FIGURE 17. 100kΩ TCv vs TAP POSITION, V CH1: 1V/DIV, 1µs/DIV CH2: 10mV/DIV, 1µs/DIV FIGURE 19. WIPER DIGITAL FEED-THROUGH 12 ISL23348 (Continued) 100 127   FIGURE 16. 50kΩ TCr vs TAP POSITION, V 100 80 ...

Page 13

... I I The high (RHi and low (RLi terminals of the ISL23348 are equivalent to the fixed terminals of a mechanical potentiometer. RHi and RLi are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WRi set to 127 decimal, the wiper will be closest to RHi, and with the WRi set to 0, the wiper is closest to RLi ...

Page 14

... WR0, Wiper Register WR1, Wiper Register WR2, Wiper Register WR3 and Access Control Register (ACR). The memory map of ISL23348 is shown in Table 1. The Wiper Register WRi at address i contains current wiper position of DCPi ( 3). The Access Control Register (ACR) at address 10h contains information and control bits described in Table 2 ...

Page 15

... Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 27). On power-up of the ISL23348, the SDA pin is in the input mode. SCL SDA START FIGURE 27 ...

Page 16

... Identification byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Identification byte with the R/W bit set to “1”. After each of the three bytes, the ISL23348 responds with an ACK; then the ISL23348 transmits Data Byte. The master terminates the read operation issuing a NACK (ACK) and a STOP condition following the last bit of the last Data Byte (see Figure 30) ...

Page 17

... V should be powered continuously during normal operation. LOGIC In a case where turning V OFF is necessary LOGIC recommended to ground the V pin of the ISL23348. LOGIC Grounding the V pin or both V LOGIC LOGIC other devices on the same bus good practice to put a 1µF cap in parallel to 0.1µF as close to the V ...

Page 18

... TOP VIEW H C SEATING PLANE 0.10 C SIDE VIEW (5.65) (0.65 TYP) TYPICAL RECOMMENDED LAND PATTERN 18 ISL23348 PIN #1 I.D. MARK 9 B 0.65 - 0.05 0.90 +0.15/-0.10 1.20 MAX 0.25 +0.05/-0. (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. ...

Page 19

... Package Outline Drawing L20.3x4 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 3/10 3. PIN 1 INDEX AREA A TOP VIEW (2.65) (3.80) (1.65) (2.80) TYPICAL RECOMMENDED LAND PATTERN 19 ISL23348 A B 20X 4 4.00 0.15 (4X) VIEW "A-A" 20x 0.40±0.10 (16 x 0.50) (20 x 0.25) (20 x 0.60) NOTES: 1. Dimensions are in millimeters. Dimensions Dimensioning and tolerancing conform to AMSE Y14.5m-1994. ...

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