isl22424 Intersil Corporation, isl22424 Datasheet
isl22424
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isl22424 Summary of contents
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... DCP’s IVRi to the corresponding WRi. The ISL22424 also has 13 General Purpose non-volatile registers that can be used as storage of lookup table for multiple wiper position or any other valuable information. The ISL22424 features a dual supply, that is beneficial for applications requiring a bipolar range for DCP terminals between V- and V . ...
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... REGISTERS RW0 GND 14 VCC SDI 11 GND 10 SCK 9 SDO 8 V- RH0 RH1 WR0 VOLATILE REGISTER AND WIPER CONTROL CIRCUITRY RL0 RW1 RL1 ISL22424 (16 LD QFN) TOP VIEW RL0 1 12 RH0 FN6425.0 ...
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... EPAD* * Note: PCB thermal land for QFN EPAD should be connected to V- plane or left floating. For more information refer to http://www.intersil.com/data/tb/TB389.pdf 3 ISL22424 SYMBOL RH0 “High” terminal of DCP0 RL0 “Low” terminal of DCP0 RW0 “Wiper” terminal of DCP0 RH1 “ ...
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... V DCP to DCP matching MATCH (Note 10) TC Ratiometric temperature coefficient V (Note 11, 20) 4 ISL22424 Thermal Information Thermal Resistance (Typical, Note 3) 14 Lead TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 +0 Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Maximum Junction Temperature (Plastic Package +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp ...
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... I V- Supply Current (non-volatile V-2 write/read) V- Supply Current (non-volatile write/read Current (standby ISL22424 TEST CONDITIONS Wiper at midpoint (80hex) W option (10k) Wiper at midpoint (80hex) U option (50k) Wiper at midpoint (80hex) T option (100k) and R with R not connected, or between option U, T option ...
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... HIGH voltage Hysteresis SCK, SDI, and CS input buffer hysteresis V SDO output buffer LOW voltage OL R SDO pull-up resistor off-chip pu (Note 19) 6 ISL22424 TEST CONDITIONS V- = -5.5V +5.5V @ +85°C, SPI interface CC in standby state V- = -5.5V +5.5V @ +125°C, SPI CC interface in standby state V- = -2.25V +2.25V @ +85°C, SPI ...
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... Write sequence of SPI serial interface, to the end of the self-timed internal non-volatile write cycle specified for the highest data rate transfer for the device. Higher value pull-up can be used at lower data rates. pu 20. This parameter is not 100% tested. 7 ISL22424 TEST CONDITIONS R = 2k, Cbus = 30pF 2k, Cbus = 30pF ...
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... SU MSB SDI HIGH IMPEDANCE SDO Output Timing CS SCK t SO MSB SDO t V ADDR SDI XDCP Timing (for All Load Instructions) CS SCK MSB SDI V W HIGH IMPEDANCE SDO 8 ISL22424 10pF t CYC ... ... t HO ... ... LSB ... ...
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... TAP POSITION (DECIMAL) FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10kΩ (W) 2.0 1.6 1.2 0.8 50k V = 2.25V CC 0 TEMPERATURE (ºC) FIGURE 5. ZS ERROR vs TEMPERATURE 9 ISL22424 2 +125ºC 1.5 1 +25ºC 0.5 -0 -40ºC -1.0 -1.5 -2.0 200 250 FIGURE 2. STANDBY I 0. +25ºC 0.25 -0.25 -0.50 200 250 FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER ...
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... FIGURE 9. END TO END R % CHANGE vs TOTAL TEMPERATURE 500 10k 400 300 200 100 116 TAP POSITION (DECIMAL) FIGURE 11. TC FOR RHEOSTAT MODE IN ppm 10 ISL22424 (Continued) 2 +25ºC 1.5 1.0 0.5 -0.5 200 250 FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR 200 10k 160 120 80 40 ...
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... CS LOW enables the ISL22424, placing it in the active power mode. A HIGH to LOW transition required prior to the start of any operation after power up. When CS is HIGH, the ISL22424 is deselected and the SDO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. ...
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... RWi and RLi increases monotonically, while the resistance between RHi and RWi decreases monotonically. While the ISL22424 is being powered up, the WRi is reset to 80h (128 decimal), which locates RWi roughly at the center between RLi and RHi. After the power supply voltage ...
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... SDO 13 ISL22424 Write Operation A Write operation to the ISL22424 is a two or more bytes operation. First, It requires, the CS transition from HIGH to LOW. Then host must send a valid Instruction Byte followed by one or more Data Bytes to SDI pin. The host terminates the write operation by pulling the CS pin from LOW to HIGH. ...
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... WRi as the IVRi. Reading from the IVRi will not change the WRi, if its contents are different. Daisy Chain Configuration When application needs more then one ISL22424, it can communicate with all of them without additional CS lines by daisy chaining the DCPs as shown on Figure 18. In Daisy ...
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... Application Example Figure 22 shows an example of using ISL22424 for gain setting and offset correction in high side current measurement application. DCP0 applies a programmable offset voltage of 25mV to the FB+ pin of the Instrumentation ± Amplifier EL8173 to adjust output offset to zero voltages. CS SCK DCP0 MOSI MISO CS SCK µ ...
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... EL8173IS IN IN OUT 7 FB RH1 RW1 2 50k RL1 DCP1 (1/2 ISL22424U) PROGRAMMABLE GAIN 90 TO 110 3 ISL22424UFV14Z 14 1 +5V Vcc RH0 2 DCP0 RL0 10 3 SCL RW0 9 SDO 4 12 RH1 SDI 5 13 DCP1 RL1 RW1 ...
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... Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) 17 ISL22424 L16.4x4A 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220-VGGD-10) MILLIMETERS SYMBOL MIN 0. θ - NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 ISL22424 M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC M ...