isl8201m Intersil Corporation, isl8201m Datasheet

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... PWM controller switching at 600kHz, power MOSFETs, an inductor, and all the passive components required for complete DC/DC power solution. The ISL8201M operates over an input voltage range 20V and supports an output voltage range of 0.6V to 5V, which is set by a single dividing resistor. This high efficiency ...

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... Simplified Block Diagram PGND ISET 0.6V FB 0.4V COMP/EN 2 ISL8201M PVCC SAMPLE POR AND AND LDO HOLD SOFT-START DRIVER - INHIBIT + 21.5µA + GATE + PWM CONTROL - LOGIC - PVCC + DIS DRIVER - OSCILLATOR PWM Controller RFB-TI FIGURE 1. INTERNAL BLOCK DIAGRAM RSET-IN ISET PHASE April 28, 2009 VIN VOUT PGND ...

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... NC 7 ISET 9 VIN 10 PHASE 12 VOUT 13 COMP/ ISL8201M ISL8201M (15 LD QFN) TOP AND 3D VIEW Power ground. Connect to ground plane directly. Supply voltage. Connect 1µF ceramic capacitor to ground plane directly. Do not connect. Overcurrent protection. Integrated internal 3.57kΩ resistor. Connect additional resistor between this pin and PGND pin can change initial setting ...

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... Shutdown PVCC Supply Current Supply Voltage P Operating Current VCC Rising P Threshold VCC P Power-On-Reset Threshold Hysteresis VCC 4 ISL8201M Thermal Information - 0.3V to +6V Thermal Resistance (Typical, Note 2) GND - 0. 0. QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND VCC - 0.3V to +15V Pb-Free Reflow Profile .see link below GND http://www.intersil.com/pbfree/Pb-FreeReflow.asp ...

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... LOAD CURRENT (A) FIGURE 2. EFFICIENCY vs LOAD CURRENT (5V 100 90 80 5.0V 70 3.3V 2. LOAD CURRENT (A) FIGURE 4. EFFICIENCY vs LOAD CURRENT (18V 5 ISL8201M = 12V 1.5V 220µFx1, 10µF/Ceramicx2 OUT IN SYMBOL CONDITIONS F (Note 3) OSC R FB-TI V (Note 3) ENDIS V (Note 3) REF 0°C to +70°C (Note 3) -40° ...

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... V = 1.5V OUT (ESR = 10mΩ), 22µF/Ceramicx3 I OUT OUT OUT C PVCC PVCC VIN ISL8201M (CER) 10µF PHASE COMP/EN 25V x2 ISET PGND FIGURE 10. TYPICAL APPLICATION = 12V 220µFx1, 10µF/Ceramicx2, C VCC IN = 0-5A (10A), Current slew rate = 2.5A/µs = 12V IN = 1.8V OUT = FIGURE 7 ...

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... PVCC (Pin 5) This pin provides the bias supply for ISL8201M, as well as the low-side MOSFET’s gate and high-side MOSFET’s gate. If PVCC rises above 6.5V, an internal 5V regulator will supply to the internal logics bias (but high-side and low-side MOSFET gate will still be sourced by PVCC) ...

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... OUT R 4.87k 3.09k FB Initialization (POR and OCP Sampling) Figure 13 shows a start-up waveform of ISL8201M. The power-on-reset (POR) function continually monitors the bias voltage at the PVCC pin. Once the rising POR threshold has exceeded 4V (V nominal), the POR function initiates PORR the overcurrent protection (OCP) sample and hold operation (while COMP/EN is ~1V) ...

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... T , and the output ramps between T 0 output is pre-biased to a voltage less than the expected value (as shown Figure 17), the ISL8201M will detect that condition. Neither internal MOSFET will turn on until the soft-start ramp voltage exceeds the output; V seamlessly ramping from there. ...

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... The low side gate driver is disabled to allow an internal 21.5µA current source to develop a voltage across R ISL8201M samples this voltage (which is referenced to the PGND pin) at the ISET pin, and holds counter and DAC combination. This sampled voltage is held internally as the overcurrent set point, for as long as power is applied, or until a new sample is taken after coming out of a shut-down ...

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... During power- 12V system, the ISL8201M starts operation just above 4V; if the supply ramp is slow, the soft-start ramp might be over well before 12V is reached. Therefore, with low side gate drive ...

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... If V powers up first, Q will be on, turning off; so the ISL8201M will start-up as soon as P up. The V trip point is 0.4V nominal wide variety ENDIS of N-MOSFET or NPN BJT or even some logic IC's can be used However, Q must be low leakage when ...

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... LOAD CURRENT (A) FIGURE 24. POWER LOSS vs LOAD CURRENT (12V 13 ISL8201M Thermal Considerations Experimental power loss curves along with θ modeling analysis can be used to evaluate the thermal consideration for the module. The derating curves are derived from the maximum power allowed while maintaining the temperature below the maximum junction temperature of +125° ...

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... Users could modify parameters according to their application. PCB Layout Pattern Design The bottom of ISL8201M is lead-frame footprint, which is attached to PCB by surface mounting process. The PCB layout pattern is shown in the Package Outline Drawing L15.15x15 on page 15. The PCB layout pattern is essentially ...

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Package Outline Drawing L15.15x15 15 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN) Rev 0, 04/09 PIN 1 1 1514 13 12 INDEX AREA Max. 0.6 15.0±0.2 TOP VIEW 5° ALL ...

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Package Boundary 3.10 2.20 1.70 0.90 0.40 0.0 0.0 0.40 0.90 1.70 2.20 3.00 4.00 8.30 TYPICAL RECOMMENDED LAND PATTERN 6.60 4.80 3.40 1.80 0.00 0.60 1.20 2.20 3.70 4.30 6.60 STENCIL PATTERN WITH ...