isl9305 Intersil Corporation, isl9305 Datasheet
isl9305
Related parts for isl9305
isl9305 Summary of contents
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... The default LDO power-up output comes with factory pre-set fixed output voltage options between 0.9V to 3.3V. The ISL9305 is available in a 4mmx4mm 16 Ld TQFN package. Related Literature • FN7724, ISL9305H Data Sheet • ...
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... C4 and C5 are 10µF/6.3V for VODCD less than 1V. Block Diagram DCDPG PGOOD WITH 1~200MS DELAY TIME UVLO VREF OSC SDAT INTERFACE SCLK 2 ISL9305 TABLE 1. TYPICAL APPLICATION PART LIST PART NUMBER SPECIFICATIONS CDRH2D14NP-1R5 1.5µH/1.80A/50mΩ GRM21BR60J106KE19L 10µF/6.3V GRM185R60J105KE26D 1µF/6.3V GRM219R60J475KE01D 4.7µF/6.3V GRM185R60J105KE26D 1µF/6.3V 1%, SMD, 0.1Ω ANALOG/LOGIC ...
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... GNDDCD2 Power ground for DCD2. 15 GNDDCD1 Power ground for DCD1. 16 SW1 Switching node for DCD1, connect to one terminal of the inductor. E-pad E-pad Exposed Pad. Connect to system ground. 3 ISL9305 ISL9305 (16 LD 4X4 TQFN) TOP VIEW VINDCD1 12 VINDCD2 FB1 FB2 ...
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... RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL9305. For more information on MSL please see techbrief TB363. 4 ...
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... Thermal Shutdown Thermal Shutdown Hysteresis DCD1 AND DCD2 FB1, FB2 Regulation Voltage FB1, FB2 Bias Current 5 ISL9305 Thermal Information (Refer to ground) Thermal Resistance (Typical TQFN Package (Notes Maximum Junction Temperature Range . . . . . . . . . . . . . .-40°C to +150°C Recommended Junction Temperature Range . . . . . . . . .-40°C to +125°C Storage Temperature Range .-65° ...
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... Lock-out Threshold Internal Peak Current Limit Dropout Voltage Power Supply Rejection Ratio Output Voltage Noise NOTE: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 6 ISL9305 = +25°C, VINDCD1 = 3.6V, VINDCD2 = 3.3V. For LDO1 and LDO2 SYMBOL TEST CONDITIONS 0.5V to 5.5V (minimal 2.3V), ...
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... Theory of Operation DCD1 and DCD2 Introduction Both the DCD1 and DCD2 converters on ISL9305 use the peak-current-mode pulse-width modulation (PWM) control scheme for fast transient response and pulse-by-pulse current limiting. Both converters are able to supply up to 800mA load current. The default output voltage ranges from 0.8V to 3.6V depending on the factory pre-set configuration and can be programmed via the I interface in the range of 0 ...
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... Board Layout Recommendations The ISL9305 is a high frequency switching charger and hence the PCB layout is a very important design practice to ensure a satisfactory performance. The power loop is composed of the output inductor L, the output capacitor C , the SW pin and the PGND pin ...
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... I C Slave Address The ISL9305 serves as a slave device and the 7-bit default chip address is 1101000, as shown in Figure 5 According to the I specifications, here the value of Bit 0 determines the direction of the message (“0” means “write” and “1” means “read”). ...
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... S – START ISL9305 P – STOP Control Registers All the registers are reset at initial start-up. DCD OUTPUT VOLTAGE CONTROL REGISTER DCD1OUT, address 0x00h; DCD2OUT, address 0x01h 10 ISL9305 DATA BYTE 1 A DATA BYTE 2 AUTO INCREMENT AUTO INCREMENT REGISTER ADDRESS REGISTER ADDRESS 2 FIGURE READ NOT SPECIFYING REGISTER ADDRESS TABLE 2 ...
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... LDO1 AND LDO2 OUTPUT VOLTAGE CONTROL REGISTERS LDO1OUT, address 0x02h and LDO2OUT, address 0x03h. 11 ISL9305 TABLE 3. DCD1 AND DCD2 OUTPUT VOLTAGE SETTING DCD OUTPUT VOLTAGE DCDOUT (V) <7:0> 20 1.625 40 21 1.650 41 22 1.675 42 23 1.700 ...
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... TABLE 6. DCD_PARAMETER REGISTER BIT NAME ACCESS RESET DCD_PHASE R DCD2_ULTRA R DCD1_ULTRA R DCD2_BLD R DCD1_BLD R DCD2_MODE R DCD1_MODE R ISL9305 TABLE 5. LDOX OUTPUT VOLTAGE SETTINGS LDO OUTPUT LDOOUT <7:0> VOLTAGE (V) <7:0> ...
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... Reserved Typical Operating Conditions VODCD1(20mV/DIV, AC-COUPLING) SW2(5V/DIV) VODCD2(20mV/DIV, AC-COUPLING) SW1(5V/DIV) FIGURE 9. DCD OUTPUT VOLTAGE RIPPLE (V DCD1 AND DCD2) 13 ISL9305 DESCRIPTION = 4.2V, FULL LOAD AT FIGURE 10. DCD OUTPUT VOLTAGE RIPPLE (V IN VODCD1(20mV/DIV, AC-COUPLING) IL1 (500mA/DIV) VODCD2(20mV/DIV, AC-COUPLING) IL2 (500mA/DIV) = 4.2V, PFM MODE) IN November 8, 2010 FN7605 ...
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... V = 5. 3.6V IN 1.78 1.77 1. 100 OUTPUT CURRENT (mA) FIGURE 15. DCD OUTPUT VOLTAGE vs LOAD (V PFM/PWM) 14 ISL9305 (Continued) = 4.2V, LOAD FIGURE 12. LDO OUTPUT TRANSIENT RESPONSE (V IN VODCD1 (2V/DIV) VOLDO1 (1V/DIV) = 4.2V, NO LOAD) FIGURE 14. DCD1 and DCD2 SWITCHING WAVEFORM ( 2.8V IN 1000 10000 = 1.2V, FIGURE 16. DCD OUTPUT VOLTAGE vs LOAD (V ...
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... OUTPUT CURRENT (mA) FIGURE 17. EFFICIENCY vs OUTPUT CURRENT (V PWM MODE PSRR 3. 2.6V 10 OUT LOAD = 300mA 0 0 FREQUENCY (kHz) FIGURE 19. RIPPLE REJECTION RATIO vs FREQUENCY 15 ISL9305 100 5. 100 1k 0.1 FIGURE 18. EFFICIENCY vs OUTPUT CURRENT (V = 1.8V, FORCED OUT ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 16 ISL9305 www.intersil.com/askourstaff For additional products, see www.intersil.com/product_tree www ...
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... Package Outline Drawing L16.4x4G 16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 4/10 4.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 17 ISL9305 4X 1.95 0.65 12X 16X ± BOTTOM VIEW 0.75 SIDE VIEW ( 12X REF ( 16X 0 ...