isl97701 Intersil Corporation, isl97701 Datasheet - Page 8

• Manufacturer Part Number: isl97701
• Description: Boost Regulator With Integrated Schottky And Input Disconnect Switch
• Manufacturer: Intersil Corporation

sequence or in some cases disable the ISL97701 boost
function as long as the fault is present.
Maximum Duty Cycle – LX
The maximum duty cycle Dmax, at which the power FET can
operate defines the upper limit of the regulator output to
input voltage ratio according to Equation 2:
In the ISL97701, D
t
If NSYNC is tied to VDD the internal oscillator defines Dmax to:
D
With external synchronization at pin NSYNC
D
The duty cycle at LX can be 0% (pulse skipping), if the
output voltage exceeds the target voltage set with the
feedback resistors.
Internal Schottky Diode – LX, V
The inductor node LX internally connects to the power FET
and to the anode of the integrated power Schottky diode.
The cathode of the diode is pin V
detector at V
and immediately disables the boost regulator if the voltage
exceeds the maximum allowable voltage.
External Synchronization Pin - NSYNC
Pin NSYNC can be used to synchronize the LX output pin with
an external clock signal in the range from 600kHz to 1.4MHz.
A frequency detector monitoring NSYNC enables external
synchronization if f(NSYNC) is higher than about 300kHz. If
the pin is e.g. static high the internal oscillator defines the LX
output frequency and phase. When externally synchronized
V
--------------- -
Undervoltage at
VDD
Overcurrent
drawn from
VDD
Overvoltage at
V
Over Temperature
on chip
OFF
V
OUT
MAX
MAX
DESCRIPTION
OUT
IN
OUT
(LX)min and the switching frequency.
FAULT
(f
(NSYNC) = 1 - t
=
OSC
------------------------- -
1 D
–
) = 1 - t
1
OUT
MAX
TABLE 1. FAULT PROTECTION
continuously monitors the cathode voltage
V(VDD) <
V(VDD)off
I(VDD
It(VDD
V(V
Vt(V
Tj > Toff
MAX
CONDITION
OFF
FAULT
OUT
OUT
OFF
(LX)min*f
OUT
is defined from the minimum off-time
OUT
) >
)err
(LX)min*f(NSYNC)
) >
)err
8
Disables I/Os and waits until
V(VDD) reaches V(VDD)on to
begin with the start-up sequence
Disables VDD
LX driver and immediately
restarts the start-up sequence
Disables VDDOUT switch and
LX driver and waits until output
voltage V(VOUT) drops to
Vt(VOUT) to restart the start-up
sequence
Disables VDD
LX driver and waits until junction
temp drops to “Ton” to restart the
start-up sequence
OSC
OUT
ISL97701 FAULT REACTION
. An overvoltage
OUT
OUT
OUT
switch and
switch and
(EQ. 2)
ISL97701
all falling edges at LX are timed from the falling edge of the
clock signal applied at NSYNC. The timing of the rising edge
at LX is defined by the boost controller.
FIGURE 16. LX SYNCHRONIZATION WITH f(SYNC) = 600kHz
FIGURE 17. LX SYNCHRONIZATION WITH f(SYNC) = 1.4MHz
FIGURE 15. NSYNC TO LX SYNCHRONIZATION DELAY
V(LX)
V(NSYNC)
V(NSYNC)
V(NSYNC)
V(LX)
V(LX)
April 23, 2007
FN6474.0