isl6336b Intersil Corporation, isl6336b Datasheet - Page 20

• Manufacturer Part Number: isl6336b
• Description: 6-phase Pwm Controller With Light Load Efficiency Enhancement And Current Monitoring
• Manufacturer: Intersil Corporation

When all conditions above are satisfied, ISL6336B begins
soft-start and ramps the output voltage to 1.1V first. After
remaining at 1.1V for some time, ISL6336B reads the VID
code at VID input pins. If the VID code is valid, ISL6336B will
regulate the output to the final VID setting. If the VID code is
an OFF code, ISL6336B will shut down, and cycling VCC,
EN_PWR or EN_VTT is needed to restart.
Soft-Start
ISL6336B based VR has 4 periods during soft-start as
shown in Figure 9. After VCC, EN_VTT and EN_PWR reach
their POR/enable thresholds, The controller will have fixed
delay period t
first soft-start ramp until the output voltage reaches 1.1V
V
voltage at 1.1V for another fixed period t
period, ISL6336B reads the VID signals. If the VID code is
valid, ISL6336B will initiate the second soft-start ramp until
the voltage reaches the VID voltage minus the offset voltage.
The soft-start time is the sum of the 4 periods as shown in
Equation 14:
t
determined by a fixed 85µs plus the time to obtain valid VID
voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to validate the VID input is 500ns.
Therefore the minimum t
During t
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator, which
is defined by a resistor R
equations are the same for the case where R
to GND or VCC. The two soft-start ramp times t
be calculated based on the Equations 15 and 16:
t
t
t
D1
SS
D2
D4
BOOT
is a fixed delay with a typical value as 1.36ms. t
=
=
=
t
1.1 R
------------------------ μs
(
----------------------------------------------------- - μs
6.25 25
D1
(
D2
voltage. Then, the controller will regulate the VR
V
VID
⋅
+
and t
⋅
FIGURE 9. SOFT-START WAVEFORMS
t
6.25 25
D2
SS
–
D1
1.1
(
+
D4
. After this delay period, the VR will begin
⋅
VOUT, 500mV/DIV
t
D3
) R
, ISL6336B digitally controls the DAC
)
t
⋅
D1
+
SS
t
EN_VTT
VR_RDY
D4
SS
)
D3
(
t
from SS pin to GND or VCC. The
D2
is about 86µs.
)
500µs/DIV
20
t
D3
t
D4
D3
t
. At the end of t
D5
SS
D2
is connected
and t
D3
(EQ. 14)
(EQ. 15)
(EQ. 16)
D4
is
can
D3
ISL6336B
For example, when VID is set to 1.5V and the R
100kΩ, the first soft-start ramp time t
second soft-start ramp time t
After the DAC voltage reaches the final VID setting,
VR_RDY will be set to high with the fixed delay t
typical value for t
the controller disregards the PSI# input and always operates
in normal CCM PWM mode.
Current Sense Output
The current sourced at the IMON pin is equal to the sensed
average current inside the ISL6336B, I
application, a resistor is placed from the IMON pin to GND to
generate a voltage which is proportional to the load current
as shown in Equation 17:
where V
resistor between IMON and GND, I
current of the converter, R
connected to the ISEN+ pin, N is the active channel number
and R
The resistor from the IMON pin to GND should be chosen to
ensure that the voltage at the IMON pin is less than 1.12V
under the maximum load current. The IMON pin voltage is
clamped at a maximum of 1.12V. Once the 1.12V threshold
is reached, an overcurrent shutdown will be initiated as
described in “Overcurrent Protection” on page 21.
A small capacitor can be placed between the IMON pin and
GND to reduce noise. In addition, some applications will
require the V
constant. The filter capacitor can be chosen appropriately
based on the R
The voltage at the IMON pin will vary linearly with output
current, as shown in Figure 10 with some tolerance. Some
applications may require the addition of a positive offset on
V
IMON
0V
0A
FIGURE 10. IMON VOLTAGE vs OUTPUT CURRENT
X
=
is the DC resistance of the current sense element.
IMON
LOAD INCREASING
R
------------------ -
IMON
N
IMON
is the voltage at the IMON pin, R
IMON
V
D5
⋅
IMON_OFS
----------------- - I
R
signal to be filtered with a minimum time
ISEN
R
is 85µs. Before VR_RDY is released,
X
value to set the desired time constant.
⋅
OUT
ISEN
D4
will be 256µs.
is the sense resistor
OUT
D2
AVG
will be 704µs and the
is the total output
. In a typical
IMON
SS
D5
. The
May 22, 2008
is set at
(EQ. 17)
is the
FN6696.0