isl6620 Intersil Corporation, isl6620 Datasheet - Page 7

• Manufacturer Part Number: isl6620
• Description: Vr11.1, 4-phase Pwm Controller With Light Load Efficiency Enhancement And Load Current Monitoring
• Manufacturer: Intersil Corporation

Power-On Reset (POR) Function
During initial start-up, the VCC voltage rise is monitored. Once
the rising VCC voltage exceeds 3.8V (typically), operation of
the driver is enabled and the PWM input signal takes control
of the gate drives. If VCC drops below the falling threshold of
3.5V (typically), operation of the driver is disabled.
Internal Bootstrap Device
ISL6620, ISL6620A features an internal bootstrap Schottky
diode. Simply adding an external capacitor across the BOOT
and PHASE pins completes the bootstrap circuit. The
bootstrap function is also designed to prevent the bootstrap
capacitor from overcharging due to the large negative swing
at the trailing-edge of the PHASE node. This reduces
voltage stress on the BOOT to PHASE pins.
The bootstrap capacitor must have a maximum voltage
rating well above the maximum voltage intended for VCC. Its
capacitance value can be estimated using Equation 1:
where Q
at V
control MOSFETs. The ΔV
allowable droop in the rail of the upper gate drive. Select
results are exemplified in Figure 2.
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency (F
layout resistance, and the selected MOSFET’s internal gate
resistance and total gate charge (Q
dissipation in the driver for a desired application is critical to
ensure safe operation. Exceeding the maximum allowable
power dissipation level may push the IC beyond the maximum
recommended operating junction temperature. The DFN
package is more suitable for high frequency applications. See
“Layout Considerations” on page 8 for thermal impedance
C
Q
BOOT_CAP
GATE
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
GS1
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
=
0.0
G1
gate-source voltage and N
20nC
Q
------------------------------ - N
G1
is the amount of gate charge per upper MOSFET
V
≥
0.1
VOLTAGE
GS1
------------------------------------- -
ΔV
•
VCC
BOOT_CAP
Q
0.2
50nC
GATE
Q
•
GATE
SW
0.3
Q1
), the output drive impedance, the
= 100nC
BOOT_CAP
ΔV
0.4
BOOT_CAP
7
0.5
G
Q1
). Calculating the power
0.6
(V)
term is defined as the
is the number of
0.7
0.8
0.9
ISL6620, ISL6620A
(EQ. 1)
1.0
improvement suggestions. The total gate drive power losses
due to the gate charge of MOSFETs and the driver’s internal
circuitry and their corresponding average driver current can
be estimated using Equations 2 and 3, respectively:
where the gate charge (Q
particular gate to source voltage (V
corresponding MOSFET data sheet; I
quiescent current with no load at both drive outputs; N
and N
respectively; UVCC and LVCC are the drive voltages for
both upper and lower FETs, respectively. The I
product is the quiescent power of the driver without a load.
The total gate drive power losses are dissipated among the
resistive components along the transition path, as outlined in
Equation 4. The drive resistance dissipates a portion of the
total gate drive power losses, the rest will be dissipated by the
external gate resistors (R
resistors (R
the typical upper and lower gate drives turn-on current paths.
P
P
P
P
R
I
DR
Qg_TOT
DR
DR_UP
DR_LOW
EXT1
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
P
P
UVCC
=
=
Qg_Q2
Qg_Q1
Q2
⎛
⎜
⎝
P
=
Q
----------------------------------------------------- -
DR_UP
=
are number of upper and lower MOSFETs,
G1
=
R
=
GI1
⎛
⎜
⎝
G1
PHASE
P
--------------------------------------
R
⎛
⎜
⎝
=
=
•
Qg_Q1
HI1
--------------------------------------
R
UVCC N
+
V
BOOT
and R
Q
-------------------------------------- - F
Q
------------------------------------- - F
HI2
R
+
GS1
R
R
-------------
R
N
G1
G2
LO1
+
HI1
P
GI1
HI1
R
Q1
DR_LOW
R
+
V
V
HI2
•
•
+
GS2
EXT1
R
GS1
GI2
•
LVCC
UVCC
P
EXT2
Qg_Q2
Q1
) of MOSFETs. Figures 3 and 4 show
G1
G1
+
+
2
+
+
2
--------------------------------------- -
R
and R
•
Q
---------------------------------------------------- -
and Q
I
•
LO1
--------------------------------------- -
R
R
+
Q
G2
LO2
EXT2
I
R
SW
•
Q
SW
R
L1
VCC
+
•
LO1
R
G
•
G2
LVCC N
R
+
•
LO2
VCC
V
G2
GS1
•
N
EXT1
GS2
R
) and the internal gate
N
C
=
R
Q
Q2
) is defined at a
EXT2
GD
Q1
G1
R
C
and V
is the driver’s total
GS
G2
•
⎞
⎟
⎠
•
⎞
⎟
⎠
+
Q2
P
---------------------
•
S
R
-------------
N
Qg_Q1
GS2
P
---------------------
⎞
⎟
⎠
Q*
GI2
Qg_Q2
Q2
2
•
D
2
VCC
F
) in the
SW
April 25, 2008
Q1
C
DS
(EQ. 4)
FN6494.0
(EQ. 2)
(EQ. 3)
Q1
+
I
Q