isl62871 Intersil Corporation, isl62871 Datasheet
isl62871
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isl62871 Summary of contents
Page 1
... Output Load up to 30A • Extremely Flexible Output Voltage Programmability - 2-Bit VID (ISL62872) Selects Four Independent Setpoint Voltages - 1-Bit VID (ISL62871) Selects Two Independent Setpoint Voltages - Simple Resistor Programming of Setpoint Voltages - Accepts External Setpoint Reference Such as DAC • ±0.75% System Accuracy: -10°C to +100°C • ...
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... NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 ISL62871, ISL62872 VCC 19 BOOT ...
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... Block Diagram FB SREF SET0 SW2 *SET1 SW3 *SET2 *VID1 VID DECODER VID0 *ISL62872 ONLY GND INT 500mV FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL62872, ISL62871 EN VCC POR RUN FAULT − COMP 100pF + V SET − SW0 SW1 − OVP + FB FAULT EXT − ...
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... GND VID1 GPIO 5 VID0 6 SREF 7 SET0 8 SET1 SET1 SET2 SET3 FIGURE 3. ISL62872 APPLICATION SCHEMATIC WITH FOUR OUTPUT VOLTAGE SETPOINTS AND RESISTOR CURRENT SENSE 4 ISL62871, ISL62872 C VCC VCC BOOT 18 UGATE 17 PHASE BOOT OCSET ...
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... R VCC +5V C PVCC GND GPIO VID0 3 SREF 4 R SET1 VCC GPIO FIGURE 4. ISL62871 APPLICATION SCHEMATIC WITH TWO OUTPUT VOLTAGE SETPOINTS AND DCR CURRENT SENSE R VCC +5V C PVCC GND GPIO VID0 3 SREF 4 R SET1 VCC GPIO FIGURE 5. ISL62871 APPLICATION SCHEMATIC WITH TWO OUTPUT VOLTAGE SETPOINTS AND RESISTOR CURRENT SENSE ...
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... FIGURE 6. ISL62872 APPLICATION SCHEMATIC WITH EXTERNAL REFERENCE INPUT AND DCR CURRENT SENSE R +5V C PVCC GND 1 EN GPIO 2 VID0 EXT_REF 3 SREF 4 VCC GPIO FIGURE 7. ISL62871 APPLICATION SCHEMATIC WITH EXTERNAL REFERENCE INPUT AND DCR CURRENT SENSE 6 ISL62871, ISL62872 R VCC C VCC VCC 19 BOOT 18 UGATE 17 PHASE ...
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... ERROR AMPLIFIER FB Input Bias Current SREF SREF Operating Voltage Range Soft-Start Current Voltage Step Current 7 ISL62871, ISL62872 Thermal Information Thermal Resistance (Typical, Note µTQFN Package . . . . . . . . . . . . . . . . . . . . . . 16 Ld µTQFN Package . . . . . . . . . . . . . . . . . . . . . . Junction Temperature Range .-55°C to +150°C Operating Temperature Range . . . . . . . . . . . . . . . .-10°C to +100°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65° ...
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... VID<0,1> Leakage Current PROTECTION OCP Threshold Voltage OCP Reference Current OCSET Input Resistance OCSET Leakage Current UVP Threshold Voltage 8 ISL62871, ISL62872 = -10°C to +100°C, unless otherwise stated +25°C, VCC = 5V. Parameters with MIN and/or MAX limits are 100% tested at A SYMBOL TEST CONDITIONS V ...
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... Voltage set-point programming resistor input. See Figure 8 on page 12 for resistor connection. SET1 (Pin 9) Voltage set-point programming resistor input. See Figure 8 on page 12 for resistor connection. 9 ISL62871, ISL62872 = -10°C to +100°C, unless otherwise stated +25°C, VCC = 5V. Parameters with MIN and/or MAX limits are 100% tested at A SYMBOL ...
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... The PVCC pin is internally connected to the anode of the Schottky boot-strap diode. Connect +5V to the PVCC pin and decouple with a 10µF MLCC to the PGND pin. See “Application Schematics” (Figures 2 and 3) on page 4. ISL62871 Functional Pin Descriptions GND (Pin 1) IC ground for bias supply and signal reference. EN (Pin 2) Enable input for the IC ...
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... V SET OUT 11 ISL62871, ISL62872 The setpoint reference voltages are programmed with resistors that use the naming convention R is the first, second, third, or fourth programming resistor connected in series starting at the SREF pin and ending at the GND pin. When one of the internal switches closes, it ...
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... SET1 SET3 ⎟ (EQ. 12) ⎠ The ISL62871 V V SET2 V COMP EA V OUT V REF 500mV + V SET − SW0 SW1 SW2 SW3 FIGURE 9. ISL62871 VOLTAGE PROGRAMMING CIRCUIT V OUT V OUT1 V OUT2 is written as SET1 ⎛ ⎞ KV SET2 ⋅ ⎜ ⎟ R ---------------------- - 1 = – SET2 ⎝ V ⎠ ...
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... SS SS SOFT ISL62871, ISL62872 Where the state of the VID inputs at the time EN is asserted - R The end of soft-start is detected by I capacitor C reference setpoint. The SSOK flag is set, the PGOOD pin goes high, and the I voltage-step current source I ± ...
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... The IC monitors the voltage of the OCSET pin and the VO pin. When the voltage of the OCSET pin is higher than the voltage of the VO pin for more than 10µs, an OCP fault latches the converter off. 14 ISL62871, ISL62872 Component Selection For R The value written as: is changing ...
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... The period and duty cycle of the ensuing PWM 3 pulses are optimized by the R modulator for the remainder 15 ISL62871, ISL62872 of the transient and work in concert with the error amplifier V to maintain output voltage regulation. Once the ERR transient has dissipated and the control loop has recovered, the PWM frequency returns to the nominal static 300KHz ...
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... DCM, reducing the light-load efficiency with unnecessary conduction loss as the low-side MOSFET sinks the inductor current. The ISL62871 and ISL62872 controllers avoid the DCM conduction loss by making the low-side MOSFET emulate the current-blocking behavior of a diode. This ...
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... R FB INT COMP 17 ISL62871, ISL62872 COMP FIGURE 13. COMPENSATION REFERENCE CIRCUIT The LC output filter has a double pole at its resonant frequency that causes rapid phase change. The R IC makes the LC output filter resemble a first order system in which the closed loop stability can be achieved with the recommended Type-II compensation network ...
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... Duty cycle is written as Equation 36 ------------------------- - ⋅ V EFF IN 18 ISL62871, ISL62872 In addition to the bulk capacitance, some low ESL ceramic capacitance is recommended to decouple between the drain of the high-side MOSFET and the source of the low-side O MOSFET. develops P-P 0.60 which is the O, 0.55 ...
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... L the gate of the MOSFET and discrete capacitors - P is the quiescent power consumption of the lower L driver - P is the quiescent power consumption of the upper U driver 19 ISL62871, ISL62872 1000 900 800 700 600 500 400 300 200 100 0.6 ...
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... The single connection point should also be where the VCC decoupling capacitor and the GND pin of the IC are connected. 20 ISL62871, ISL62872 Power Ground Anywhere not within the analog-ground island is Power Ground. VCC and PVCC Pins Place the decoupling capacitors as close as practical to the IC ...
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... V = 19V IN 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1 (A) OUT FIGURE 20. SWITCHING FREQUENCY SREF V OUT FIGURE 22. START-UP INTO 750mV PRE-BIASED OUTPUT 12.6V 1.05V, LOAD = 10A IN OUT 21 ISL62871, ISL62872 19V IN -0.2 -0.4 -0.6 -0.8 -1 1.1V OUT V = 12. 1.1V FIGURE 21. START-UP, V OUT PGOOD FIGURE 23 ...
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... OUT 11ADC I OUT +10AµF -10AµF V 1ADC OUT PHASE FIGURE 28. DCM LOAD TRANSIENT RESPONSE V = 12.6V 1.0V IN OUT 22 ISL62871, ISL62872 (Continued) SREF V OUT = 1.05V, FIGURE 25. CCM STEADY-STATE OPERATION, OUT 5ADC FIGURE 27. CCM LOAD TRANSIENT RESPONSE = 3A OUT V OUT 1ADC VID0 VID1 FIGURE 29. VID TO SREF RESPONSE ...
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... Typical Performance Curves V OUT SREF VID0 VID1 FIGURE 30. SREF FALLING RESPONSE V = 12.6V 1.05V TO 950mV OUT 23 ISL62871, ISL62872 (Continued) VID0 VID1 FIGURE 31. SREF RISING RESPONSE = 10A OUT V OUT SREF VID0 VID1 FIGURE 32. VID TO SREF RESPONSE IN DCM V = 12.6V 950mV AND 1.05V ...
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... L20.3.2x1.8 20 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (UTQFN) Rev 0, 5/08 1.80 6 PIN 1 ID# (4X) 0.10 TOP VIEW (1 x 0.70 TYPICAL RECOMMENDED LAND PATTERN 24 ISL62871, ISL62872 A B VIEW “A-A” ( 1.0 ) MAX 0. 20X 19X NOTES: 1. Dimensions are in millimeters. Dimensions ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 25 ISL62871, ISL62872 L16.2.6x1. ...