isl62881 Intersil Corporation, isl62881 Datasheet - Page 12

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isl62881

Manufacturer Part Number
isl62881
Description
Single-phase Pwm Regulator For Imvp-6.5? Mobile Cpus And Gpus
Manufacturer
Intersil Corporation
Datasheet

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Diode Emulation and Period Stretching
ISL62881 can operate in diode emulation (DE) mode to
improve light load efficiency. In DE mode, the low-side
MOSFET conducts when the current is flowing from
source to drain and doesn’t not allow reverse current,
emulating a diode. As shown in Figure 8, when LGATE is
on, the low-side MOSFET carries current, creating
negative voltage on the phase node due to the voltage
drop across the ON-resistance. The ISL62881 monitors
the current through monitoring the phase node voltage.
It turns off LGATE when the phase node voltage reaches
zero to prevent the inductor current from reversing the
direction and creating unnecessary power loss.
If the load current is light enough, as Figure 9 shows, the
inductor current will reach and stay at zero before the
next phase node pulse, and the regulator is in
discontinuous conduction mode (DCM). If the load
current is heavy enough, the inductor current will never
reach 0A, and the regulator is in CCM although the
controller is in DE mode.
VCRS
VCRS
VCRS
U G A T E
P H A S E
L G A T E
IL
IL
IL
I L
FIGURE 9. PERIOD STRETCHING
FIGURE 8. DIODE EMULATION
CCM/DCM BOUNDARY
VW
VW
VW
LIGHT DCM
DEEP DCM
12
ISL62881, ISL62881B
FIGURE 10. SOFT-START WAVEFORMS FOR CPU VR
FIGURE 11. SOFT-START WAVEFORMS FOR GPU VR
Figure 9 shows the operation principle in diode emulation
mode at light load. The load gets incrementally lighter in
the three cases from top to bottom. The PWM on-time is
determined by the VW window size, therefore is the
same, making the inductor current triangle the same in
the three cases. The ISL62881 clamps the ripple
capacitor voltage V
inductor current. It takes the COMP voltage longer to hit
V
inductor current triangles move further apart from each
other such that the inductor current average value is
equal to the load current. The reduced switching
frequency helps increase light load efficiency.
Start-up Timing
With the controller's V
threshold, the start-up sequence begins when VR_ON
exceeds the 3.3V logic high threshold.
Figure 10 shows the typical start-up timing when the
ISL62881 is configured for CPU VR application. The
ISL62881 uses digital soft-start to ramp up DAC to the
boot voltage of 1.1V at about 2.5mV/µs. Once the output
voltage is within 10% of the boot voltage for 13 PWM
cycles (43µs for frequency = 300kHz), CLK_EN# is
pulled low and DAC slews at 5mV/µs to the voltage set
by the VID pins. PGOOD is asserted high in
approximately 7ms. Similar results occur if VR_ON is tied
CLK_EN#
CLK_EN#
crs
PGOOD
PGOOD
VR_ON
VR_ON
, naturally stretching the switching period. The
VDD
VDD
DAC
DAC
13 SWITCHING CYCLES
APPLICATION
APPLICATION
800µs
120µs
13 SWITCHING CYCLES
crs
5mV/µs
2.5mV/µs
DD
in DE mode to make it mimic the
90%
voltage above the POR
90%
VID COMMAND VOLTAGE
5mV/µs
VBOOT
~7ms
~7ms
VID
COMMAND
VOLTAGE
October 26, 2009
FN6924.0

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