isl6265a Intersil Corporation, isl6265a Datasheet
isl6265a
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isl6265a Summary of contents
Page 1
... ISL6265AHRTZ 6265A HRTZ -10 to +100 48 Ld 6x6 TQFN L48.6x6 ISL6265AHRTZ-T* 6265A HRTZ -10 to +100 48 Ld 6x6 TQFN *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, ...
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... RBIAS VW0 COMP0 FB0 VDIFF0 V0 VSEN0 1 RTN0 DROOP ISP0 CURRENT SENSE ISN0 ISP1 CURRENT SENSE ISN1 V1 VSEN1 1 RTN1 VDIFF1 FIGURE 1. SIMPLIFIED FUNCTION BLOCK DIAGRAM OF ISL6265A 2 ISL6265A FB_NB COMP_NB VSEN_NB VNB 1 3.0kΩ 1.5kΩ E/A VREF_NB FLT VNB FAULT RTN1 V0 PROTECTION V1 ISEN0 ISEN1 E/A I_OFS ...
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... Simplified Application Circuit for Dual Plane and Northbridge Support SVI DATA SVI CLOCK ENABLE PWROK VDDPWRGD REMOTE SENSE REMOTE SENSE VDD_PLANE_STRAP FIGURE 2. ISL6265A BASED DUAL-PLANE AND NORTHBRIDGE CONVERTERS WITH INDUCTOR DCR CURRENT SENSING 3 ISL6265A VIN +5V VIN VCC PVCC GND SVD SVC ...
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... OFS/VFIXEN VDIFF0 FB0 COMP0 VW0 VDIFF1 OPEN OPEN FB1 COMP1 OPEN OPEN VW1 FSET_NB COMP_NB FB_NB FIGURE 3. ISL6265A BASED UNIPLANE AND NORTHBRIDGE CONVERTERS WITH INDUCTOR DCR CURRENT SENSING 4 ISL6265A VIN +5V VCC PVCC GND UGATE0 BOOT0 PHASE0 LGATE0 PGND0 ISP0 ISN0 RBIAS ...
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... DNP UNIPLANE SENSE VSEN1 OFS/VFIXEN VDIFF0 FB0 COMP0 VW0 VDIFF1 FB1 COMP1 VW1 FSET_NB COMP_NB FB_NB FIGURE 4. ISL6265A BASED UNIPLANE OR DUAL PLANE CORE CONVERTER WITH INDUCTOR DCR CURRENT SENSING 5 ISL6265A VIN VCC PVCC GND UGATE0 BOOT0 PHASE0 LGATE0 PGND0 ISP0 ISN0 RBIAS ...
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... AMPLIFIERS Error Amp DC Gain (Note 3) Error Amp Gain-Bandwidth Product (Note 3) Error Amp Slew Rate (Note 3) 6 ISL6265A Thermal Information Thermal Resistance (Typical, Notes 1, 2) θ TQFN . . . . . . . . . . . . . . . . . . . . Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile .see link below http://www ...
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... LGATE Sink Current (Note 4) I SNK(LGATE) UGATE to PHASE Resistance R GATE DRIVER SWITCHING TIMING (Refer to “ISL6265A Gate Driver Timing Diagram” on page 8) UGATE Rise Time (Note 3) LGATE Rise Time (Note 3) UGATE Fall Time (Note 3) LGATE Fall Time (Note 3) UGATE Turn-on Propagation Delay ...
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... Schmitt Trigger Input Hysteresis SVD Low Level Output Voltage SVC, SVD Leakage DIFF AMP Accuracy NOTES: 3. Limits should be considered typical and are not production tested. 4. Limits established by characterization and are not production tested. ISL6265A Gate Driver Timing Diagram PWM t PDHU UGATE LGATE 1V t ...
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... PVCC The power supply pin for the internal MOSFET gate drivers of the ISL6265A. Connect this pin to a +5V power supply. Decouple this pin with a quality 1.0µF ceramic capacitor. GND The bias and reference ground for the IC. The GND connection for the ISL6265A is through the thermal pad on the bottom of the package ...
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... The return path of the lower gate driver for CORE_0 and CORE_1 respectively. Connect these pins to the corresponding sources of the lower MOSFETs. Theory of Operation The ISL6265A is a flexible multi-output controller supporting Northbridge and single or dual power planes required by Class M AMD Mobile CPUs. In single plane applications, both core voltage regulators operate single-phase. In uniplane core applications, the core voltage regulators are configured to operate as a two-phase regulator ...
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... FIGURE 6. MODULATOR WAVEFORMS DURING LOAD Power-On Reset The ISL6265A requires a +5V input supply tied to VCC and PVCC to exceed a rising power-on reset (POR) threshold before the controller has sufficient bias to guarantee proper operation. Once this threshold is reached or exceeded, the ISL6265A has enough bias to begin checking RTN1, OFS/VFIXEN, ENABLE, and SVI inputs ...
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... Interval locks core output configuration and pre-Metal VID code. All outputs soft-start to this level. Interval PGOOD signal goes HIGH indicating proper operation. Interval CPU detects VDDPWRGD high and drives PWROK high to allow ISL6265A to prepare for SVI code. Interval SVC and SVD data lines communicate change in VID code. ...
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... VID transition. The AMD requirements under these conditions do not require the regulator to meet the minimum slew rate specification of -5mV/µs. In either case, the slew rate is not allowed to exceed 10mV/µs. The ISL6265A does not change the state of PGOOD (VDDPWRGD in AMD specifications) when a VID-on-the-fly transition occurs. ...
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... NOTE: Indicates a VID not required for AMD Family 10h processors. 14 ISL6265A TABLE 3. SERIAL VID CODES VOLTAGE VOLTAGE (V) SVID[6:0] 1.1500 100_0000b 0.7500 1.1375 100_0001b 0.7375 1.1250 100_0010b 0.7250 1.1125 100_0011b ...
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... The processor then sends the PSI-L bit and VID bits during the data phase. The Serial VID 8-bit data field encoding is outlined in Table 5. If ISL6265A receives a valid 8-bit code during the data phase, it sends the acknowledge bit. Finally, the processor sends the stop sequence ...
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... Core and Northbridge regulators feature two different types of current sense circuits. CORE CONTINUOUS CURRENT SENSE The ISL6265A provides for load current to be measured using either resistors in series with the individual output inductors or using the intrinsic series resistance of the inductors as shown in the applications circuits in Figures 2 and 3 ...
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... Conversely, when the low-side MOSFET conducts negative (EQ. 11) inductor current, the phase voltage is positive with respect to the GND and PGND pins. The ISL6265A monitors the phase voltage when the low-side MOSFET is conducting inductor current to determine the direction of the inductor current. When the output load current is less than half the inductor ripple current, the inductor current goes negative ...
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... Power-Good Signal The power-good pin (PGOOD open-drain logic output that signals if the ISL6265A is not regulating Core and Northbridge output voltages within the proper levels output current in one or more outputs has exceeded the maximum current setpoint ...
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... The ISL6265A monitors the individual Core and Northbridge output voltages using differential remote sense amplifiers. level range will The ISL6265A features a severe overvoltage (OV) threshold of 1.8V. If any of the outputs exceed this voltage fault is immediately triggered. PGOOD is latched low and the low-side MOSFETs of the offending output(s) are turned on. ...
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... Take into account that the rated value capacitor can degrade as much as 50% as the DC voltage across it increases. 20 ISL6265A Selection of the Input Capacitor The input capacitors are responsible for sourcing the AC component of the input current flowing into the upper MOSFETs. Their RMS current capability must be sufficient to ...
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... I is the sum of the DC component of the inductor PEAK current plus 1/2 of the inductor ripple current 21 ISL6265A - t saturation - t Selecting The Bootstrap Capacitor All three integrated drivers feature an internal bootstrap schottky diode. Simply adding an external capacitor across ...
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... The bottom of the ISL6265A QFN package is the signal ground (GND) terminal for analog and logic signals of the IC. Connect the GND pad of the ISL6265A to the island of ground plane under the top layer using several vias, for a robust thermal and electrical conduction path. Connect the input capacitors, the output capacitors, and the source of the lower MOSFETs to the power ground plane ...
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... Package Outline Drawing L48.6x6 48 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 4/07 6.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( 5. 75 TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 23 ISL6265A 48X 0.45 ± 0.10 BOTTOM VIEW MAX 0. SIDE VIEW REF ( 48X 48X DETAIL " ...