isl6260c Intersil Corporation, isl6260c Datasheet - Page 19

• Manufacturer Part Number: isl6260c
• Description: Multiphase Pwm Regulator For Imvp-6 Mobile Cpus
• Manufacturer: Intersil Corporation

IMVP-6
Logic
Other
Logic
Modes of Operation Programmed by Logic Signals
The operational modes of ISL6260C are programmed by the
control signals of DPRSLPVR, DPRSTP#, and PSI#.
ISL6260C responds PSI# signal by adding or dropping
PWM2 and adjusting the overcurrent protection level
accordingly. For example, if the ISL6260C is initially used as
three phase controller, the PSI# signal will add or drop
PWM2 and leave PWM1 and PWM3 always in operation.
Meanwhile, after PWM2 is dropped, the phase shift between
the PWM1 and PWM3 is adjusted from 120° to 180° and the
overcurrent and the way-overcurrent protection level will be
adjusted to 2/3 of the initial value. If the ISL6260C is initially
used as two phase operation, it is suggested that PWM1 and
PWM2 pair, not PWM1 and PWM3 pair, should be used such
that the PSI# signal will enable or disable PWM2 with PWM1
in operation always. The overcurrent and way-overcurrent
protection level in two-to-one phase mode operation will be
adjusted as two-to-one as well.
The DCM mode operation is independent of PSI# for
ISL6260C. It responds to the DPRSLPVR and DPRSTP#.
Table 2 shows the operation modes of ISL6260C with
combinations of control logic.
When PSI# is de-asserted low, ISEN2 pin is connected to
the ISEN pins of the operational phases internally to keep
proper current balance and minimize the inductor current
overshoot and undershoot when the disabled phase is
enabled again.
Protection
The ISL6260C provides overcurrent, overvoltage, and
undervoltage protection. Overcurrent protection is related to
the voltage droop which is determined by the load line
requirement. After the load-line is set, the OCSET resistor can
be selected to detect overcurrent at any level of droop voltage.
For overcurrent less that 2.5x the OCSET level, the overload
condition must exist for 120µs in order to trip the OC fault
latch. This is shown in Figure 28.
DPRSLPVR DPRSTP# PSI#
TABLE 2. ISL6260C MODE OF OPERATIONS
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
19
1
0
1
0
1
0
1
0
N phase CCM
N-1 phase CCM Active
N phase DCM
N-1 phase DCM Deeper
N phase CCM
N-1 phase CCM
N phase CCM
N-1phase CCM
OPERATION
MODE OF
Active
Deeper
sleep
sleep
MODE
CPU
ISL6260C
For overload exceeding 2.5 times the OCSET level, the
PWM outputs will immediately shut off and PGOOD will go
low to maximize protection due to hard short circuit. This
protection was referred to as way-overcurrent or fast over
current, for short-circuit protections.
In addition, excessive phase unbalance due to gate driver
failure will be detected and will shut down the controller. The
phase unbalance is detected by the voltage on the ISEN pin.
If the ISEN pin voltage difference is greater than 9mV for 1ms,
the controller will latch off.
Undervoltage protection is independent of the overcurrent
limit. If the output voltage is less than the VID set value by
300mV or more, a fault will latch after 1ms in that condition.
The PWM outputs will turn off and PGOOD will go low. This
is shown in Figure 27. Note that most practical core voltage
regulators will have the overcurrent set to trip before the
-300mV undervoltage limit.
There are two levels of overvoltage protection with different
response. The first level of overvoltage protection is referred
to as PGOOD overvoltage protection. Basically, for output
voltage exceeding the set value by +200mV for 1ms, a fault
will be declared with PGOOD latched low.
All of the above faults have the same action taken: PGOOD
is latched low and the upper and lower power FETs are
turned off so that inductor current will decay through the FET
body diodes. This condition can be reset by bringing VR_ON
low or by bringing V
inputs are returned to their high operating levels, a soft-start
will occur.
The second level of overvoltage protection behaves
differently. If the output exceeds 1.7V, an OV fault is
immediately declared, PGOOD is latched low and the
low-side FETs are turned on. The low-side FETs will remain
on until the output voltage is pulled down below 0.85V at
which time all FETs are turned off. If the output again rises
above 1.7V, the process is repeated. This affords the
maximum amount of protection against a shorted high-side
FET while preventing output ringing below ground. The 1.7V
OVP can not be reset with VR_ON, but requires that V
lowered to reset. The 1.7V OV detector is active at all times
when the controller is enabled including after one of the
other faults occurs. This ensures the processor is protected
against high-side FET leakage while the FETs are
commanded off.
DD
below POR threshold. When these
March 6, 2009
FN9259.2
DD
be