isl6263c Intersil Corporation, isl6263c Datasheet - Page 9

• Manufacturer Part Number: isl6263c
• Description: 5-bit Vid Single-phase Voltage Regulator With Current Monitor For Gpu Core Power
• Manufacturer: Intersil Corporation

Theory of Operation
The R
The heart of the ISL6263C is Intersil’s Robust-Ripple-
Regulator (R
of fixed frequency PWM control, and variable frequency
hysteretic control that will simultaneously affect the PWM
switching frequency and PWM duty cycle in response to
input voltage and output load transients.
The term “Ripple” in the name “Robust-Ripple-Regulator”
refers to the synthesized voltage-ripple signal V
appears across the internal ripple-capacitor C
signal is a representation of the output inductor ripple
current. Transconductance amplifiers measuring the input
voltage of the converter and the output set-point voltage
V
A voltage window signal V
COMP pins by sourcing a current proportional to g
through a parallel network consisting of resistor R
capacitor C
along with similar companion signals are converted into
PWM pulses.
The PWM frequency is proportional to the difference in
amplitude between V
large-amplitude, low noise synthesized signals allows the
ISL6263C to achieve lower output ripple and lower phase
jitter than either conventional hysteretic or fixed frequency
PWM controllers. Unlike conventional hysteretic converters,
the ISL6263C has an error amplifier that allows the controller
to maintain tight voltage regulation accuracy throughout the
VID range from 0.41200V to 1.28750V.
Voltage Programming
The output voltage V
voltage, V
DAC output voltage is programmed by the external five VID
pins. Refer to Table 1 for the VID voltage programming
specification.
Power-On Reset
The ISL6263C is disabled until the voltage at the VDD pin
has increased above the rising VDD power-on reset (POR)
V
disabled when the voltage at the VDD pin decreases below
the falling POR V
Start-Up Timing
Figure 4 shows the ISL6263C start-up timing. Once VDD
has ramped above V
by pulling the VR_ON pin voltage above the input-high
threshold V
capacitor C
set-point as it is charged by the soft-start current source I
The V
voltage ramp to within 10% of the VID set-point then counts
SOFT
DD_THR
OUT
, together produce the voltage-ripple signal V
3
Modulator
SOFT
threshold voltage. The controller will become
output voltage of the converter follows the V
VR_ONH
FSET.
SOFT
3
) Technology™. The R
, which is determined by the DAC output. The
DD_THF
The synthesized voltage-ripple signal V
begins slewing to the designated VID
. Approximately 100µs later, the soft-start
OUT
DD_THR
W
and V
is regulated to the SOFT pin
threshold voltage.
W
is created across the VW and
, the controller can be enabled
COMP
9
. Operating on these
3
modulator is a hybrid
R.
R
The V
FSET
that
m
R
V
.
SOFT
R
SOFT
and
SS
R
ISL6263C
.
13 switching cycles, then changes the open-drain output of
the PGOOD pin to high impedance. During soft-start, the
regulator always operates in continuous conduction mode
(CCM).
MODE
GPU
TABLE 1. VID AND DAC TRUTH TABLE
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
VID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
-
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
-
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
-
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
-
1.28750V
1.26175V
1.23600V
1.21025V
1.18450V
1.15875V
1.13300V
1.10725V
1.08150V
1.05575V
1.03000V
1.00425V
0.97850V
0.95275V
0.92700V
0.90125V
0.87550V
0.84975V
0.82400V
0.79825V
0.77250V
0.74675V
0.72100V
0.69525V
0.66950V
0.64375V
0.61800V
0.59225V
0.56650V
0.54075V
0.51500V
0.41200V
V
(DAC)
July 31, 2008
SOFT
0V
FN6745.0