isl6551irec Intersil Corporation, isl6551irec Datasheet - Page 10

• Manufacturer Part Number: isl6551irec
• Description: Zvs Full Bridge Pwm Controller
• Manufacturer: Intersil Corporation

• VDDP1 and VDDP2 are the bias supplies for the upper
• Heavy copper should be attached to these pins for a better
IC GNDs (VSS, PGND)
• VSS is the reference ground, the return of VDD, of all control
• PGND is the power return, the high-current return path of both
• Copper planes should be attached to both pins.
Undervoltage Lockout (UVLO)
• UVLO establishes an orderly start-up and verifies that VDD is
• UVLO limits are not applicable to VDDP1 and VDDP2.
Bandgap Reference (BGREF)
• The reference voltage VREF is generated by a precision
• This pin must be pulled up to VDD with a resistance of
drivers and the lower drivers, respectively. They should be
decoupled with ceramic capacitors to the PGND pin.
heat spreading.
circuits and must be kept away from nodes with switching
noises. It should be connected to the PGND in only one
location as close to the IC as practical. For a secondary side
control system, it should be connected to the net after the
output capacitors, i.e., the output return pinout(s). For a
primary side control system, it should be connected to the net
before the input capacitors, i.e., the input return pinout(s).
VDDP1 and VDDP2. It should be connected to the SOURCE
pins of two lower power switches or the RETURNs of external
drivers as close as possible with heavy copper traces.
above the turn-on threshold voltage (VDD
are held low during the lockout. UVLO incorporates
hysteresis VDD
while powering up.
bandgap circuit.
approximately 399kΩ for proper operation. For additional
reference loads (no more than 1mA), this pull-up resistor
should be scaled accordingly.
CT
RD
CT
RD
HYS
to prevent multiple startup/shutdowns
I_CT
I_CT
10
VDD -
VMAX
VMIN
DEAD TIME (DT)
FIGURE 2. SIMPLIFIED CLOCK GENERATOR CIRCUIT
SET CLOCK
ON
). All the drivers
-
+
-
+
OUT
OUT
ISL6551IREC
• This pin must also be decoupled with an 0.1µF low ESR
Clock Generator (CT, RD)
• This free-running oscillator is set by two external
• The switching frequency (Fsw) of the power train is half of the
R
S
ceramic capacitor.
components, as shown in Figure 2. A capacitor at CT is
charged and discharged with two equal constant current
sources and fed into a window comparator to set the clock
frequency. A resistor at RD sets the clock dead time. RD and
CT should be tied to the VSS pin on their other ends as close
as possible. The corresponding CT for a particular frequency
can be selected from Figure 1.
clock frequency (Fclock), as shown in Equation 1.
3,000
2,500
2,000
1,500
1,000
500
Fsw
Q
Q
0
10
+60°C
+120°C
+0°C
Q
=
Fclock
------------------ -
2
FIGURE 1. CT vs FREQUENCY
CLK
Q
RECOMMENDED RANGE
100
DT
CT (pF)
1,000
DT
September 2, 2008
10,000
CLK
(EQ. 1)
FN6762.0