isl6566a Intersil Corporation, isl6566a Datasheet - Page 19

• Manufacturer Part Number: isl6566a
• Description: Three-phase Buck Pwm Controller With Two Integrated Mosfet Drivers And One External Driver Signal
• Manufacturer: Intersil Corporation

General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multi-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and example
board layouts for all common microprocessor applications.
Power Stages
The first step in designing a multi-phase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis which in turn depends
on system constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board, whether through-hole components are permitted, the
total board space available for power-supply circuitry, and
the maximum amount of load current. Generally speaking,
the most economical solutions are those in which each
phase handles between 25 and 30A. All surface-mount
designs will tend toward the lower end of this current range.
If through-hole MOSFETs and inductors can be used, higher
per-phase currents are possible. In cases where board
space is the limiting constraint, current can be pushed as
high as 40A per phase, but these designs require heat sinks
and forced air to cool the MOSFETs, inductors and heat-
dissipating surfaces.
MOSFETS
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct, the switching frequency,
the capability of the MOSFETs to dissipate heat, and the
availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for power loss in the lower MOSFET is
simple, since virtually all of the loss in the lower MOSFET is
FIGURE 14. OVERCURRENT BEHAVIOR IN HICCUP MODE
0A
0V
OUTPUT CURRENT, 50A/DIV
OUTPUT VOLTAGE,
500mV/DIV
F
SW
= 500kHz
2ms/DIV
19
ISL6566A
due to current conducted through the channel resistance
(r
output current, I
Equation 1), and d is the duty cycle (V
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I
frequency, f
the beginning and the end of the lower-MOSFET conduction
interval respectively.
The total maximum power dissipated in each lower MOSFET
is approximated by the summation of P
UPPER MOSFET POWER CALCULATION
In addition to r
MOSFET losses are due to currents conducted across the
input voltage (V
higher portion of the upper-MOSFET losses are dependent
on switching frequency, the power calculation is more
complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times, the lower-MOSFET body-diode reverse-
recovery charge, Q
conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 17,
the required time for this commutation is t
approximated associated power loss is P
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t
approximate power loss is P
A third component involves the lower MOSFET reverse-
recovery charge, Q
commutated to the upper MOSFET before the lower-
MOSFET body diode can recover all of Q
P
P
P
P
P
DS(ON)
LOW 1
LOW 2
UP 1 ,
UP 2 ,
UP 2 ,
,
,
≈
≈
≈
V
V
V
). In Equation 15, I
=
=
IN
IN
IN
r
V


S




DS ON
D ON
I
----- -
N
I
I
----- -
----- -
, and the length of dead times, t
N
N
M
M
M
(
DS(ON)
(
+
–
–
IN
PP
I
-------- -
I
I
-------- -
-------- -
)
PP
PP
PP
) during switching. Since a substantially
2
2
2
)
f
S
is the peak-to-peak inductor current (see
rr
rr



 t

 t
 t


, and the upper MOSFET r
. Since the inductor current has fully
I
----- -
N









M


losses, a large portion of the upper-
----
----
----
I
----- -
2
2
2



N
2
2
1
M
2









(
+
M
f
f
f
1 d
S
S
S
I
-------- -
, V
M
–
PP
2
UP,2
is the maximum continuous
2
D(ON)
 t

)
. In Equation 18, the
+
d1
.
I
--------------------------------
L PP
,
+
2
, the switching



12
I
----- -
OUT
(
N
M
1 d
LOW,1
–
–
UP,1
rr
1
I
-------- -
/V
, it is conducted
PP
2
and the
)
IN
d1



.
and P
).
t
DS(ON)
d2
and t
July 27, 2005
LOW,2
d2
(EQ. 15)
(EQ. 16)
(EQ. 17)
(EQ. 18)
FN9200.2
, at
.