SSTUB32865 NXP Semiconductors, SSTUB32865 Datasheet

SSTUB32865

Manufacturer Part Number

SSTUB32865

Description

Sstub32865 1.8 V 28-bit 1 2 Registered Buffer With Parity For Ddr2-800 Rdimm Applications

Manufacturer

NXP Semiconductors

Datasheet

1.SSTUB32865.pdf (28 pages)

Available stocks

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Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

SSTUB32865ET/G,518

Manufacturer:

NXP Semiconductors

Quantity:

10 000

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1. General description

2. Features

The SSTUB32865 is a 1.8 V 28-bit 1 : 2 register speciﬁcally designed for use on two rank

by four (2R

is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the

functionality of the normally required two registers in a single package, thereby freeing up

board real-estate and facilitating routing to accommodate high-density Dual In-line

Memory Module (DIMM) designs.

The SSTUB32865 also integrates a parity function, which accepts a parity bit from the

memory controller, compares it with the data received on the D-inputs and indicates

whether a parity error has occurred on its open-drain PTYERR pin (active LOW).

It further offers added features over the JEDEC standard register in that it can be

conﬁgured for normal or high output drive strength, simply by tying input pin SELDR either

HIGH of LOW as needed. This allows use in different module designs varying from low to

high density designs by picking the appropriate drive strength to match net loading

conditions. Furthermore, the SSTUB32865 features two additional chip select inputs,

which allow more versatile enabling and disabling in densely populated memory modules.

Both added features (drive strength and chip selects) are fully backward compatible to the

JEDEC standard register.

The SSTUB32865 is packaged in a 160-ball, 12

ﬁne-pitch ball grid array (TFBGA) package, which, while requiring a minimum

9 mm

conventional card technology.

SSTUB32865

1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800

RDIMM applications

Rev. 03 — 27 March 2007

28-bit data register supporting DDR2

Fully compliant to JEDEC standard for SSTUB32865

Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two

JEDEC-standard DDR2 registers (that is, 2

Parity checking function across 22 input data bits

Parity out signal

Controlled multi-impedance output impedance drivers enable optimal signal integrity

and speed

Meets or exceeds SSTUB32865 JEDEC standard speed performance

Supports up to 450 MHz clock frequency of operation

Programmable for normal or high output drive

Optimized pinout for high-density DDR2 module design

13 mm of board space, allows for adequate signal routing and escape using

4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It

SSTUB32864 or 2

18 grid, 0.65 mm ball pitch, thin proﬁle

Product data sheet

SSTUB32866)

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