SST25VF064C Silicon Storage Technology, Inc., SST25VF064C Datasheet - Page 4

• Manufacturer Part Number: SST25VF064C
• Description: 64 Mbit Spi Serial Dual I/o Flash
• Manufacturer: Silicon Storage Technology, Inc.

Data Sheet
MEMORY ORGANIZATION
The SST25VF064C SuperFlash memory array is orga-
nized in uniform 4 KByte erasable sectors with 32 KByte
overlay blocks and 64 KByte overlay erasable blocks.
DEVICE OPERATION
The SST25VF064C is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI bus
consists of four control lines; Chip Enable (CE#) is used to
select the device, and data is accessed through the Serial
Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK).
©2009 Silicon Storage Technology, Inc.
FIGURE 3: SPI Protocol
SCK
CE#
SO
SI
MODE 3
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
HIGH IMPEDANCE
4
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
The SST25VF064C supports both Mode 0 (0,0) and Mode
3 (1,1) of SPI bus operations. The difference between the
two modes, as shown in Figure 3, is the state of the SCK
signal when the bus master is in Stand-by mode and no
data is being transferred. The SCK signal is low for Mode 0
and SCK signal is high for Mode 3. For both modes, the
Serial Data In (SI) is sampled at the rising edge of the SCK
clock signal and the Serial Data Output (SO) is driven after
the falling edge of the SCK clock signal.
64 Mbit SPI Serial Dual I/O Flash
DON'T CARE
MODE 3
MODE 0
SST25VF064C
S71392-01-000
1392 F04.0
4/09