SST25VF032B Silicon Storage Technology, Inc., SST25VF032B Datasheet - Page 17

• Manufacturer Part Number: SST25VF032B
• Description: 32 Mbit Spi Serial Flash
• Manufacturer: Silicon Storage Technology, Inc.

32 Mbit SPI Serial Flash
SST25VF032B
Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the Write-
Enable-Latch bit in the Status Register to ‘1’ allowing Write
operations to occur. The WREN instruction must be exe-
cuted prior to any Write (Program/Erase) operation. The
WREN instruction may also be used to allow execution of
the Write-Status-Register (WRSR) instruction; however,
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the Write-
Enable-Latch bit and AAI bit to ‘0,’ therefore, preventing any
new Write operations. The WRDI instruction will not termi-
nate any programming operation in progress. Any program
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction
arms the Write-Status-Register (WRSR) instruction and
opens the status register for alteration. The Write-Status-
Register instruction must be executed immediately after the
execution of the Enable-Write-Status-Register instruction.
This two-step instruction sequence of the EWSR instruc-
tion followed by the WRSR instruction works like software
data protection (SDP) command structure which prevents
any accidental alteration of the status register values. CE#
©2008 Silicon Storage Technology, Inc.
FIGURE 18: Write Enable (WREN) Sequence
FIGURE 19: Write Disable (WRDI) Sequence
SCK
CE#
SCK
CE#
SO
SO
SI
SI
MODE 3
MODE 0
MODE 3
MODE 0
HIGH IMPEDANCE
HIGH IMPEDANCE
MSB
0 1 2 3 4 5 6 7
MSB
0 1 2 3 4 5 6 7
17
the Write-Enable-Latch bit in the Status Register will be
cleared upon the rising edge CE# of the WRSR instruction.
CE# must be driven high before the WREN instruction is
executed.
operation in progress may continue up to T
ing the WRDI instruction. CE# must be driven high before
the WRDI instruction is executed.
must be driven low before the EWSR instruction is entered
and must be driven high before the EWSR instruction is
executed.
04
06
1327 F19.0
1327 F18.0
Advance Information
S71327-01-000
BP
after execut-
4/08