S25FL064K Meet Spansion Inc., S25FL064K Datasheet - Page 18

• Manufacturer Part Number: S25FL064K
• Description: 64-mbit Cmos 3.0 Volt Flash Memory With 80-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

7. Instructions
18
Notes:
1. X = don’t care
2. L = Lower; U = Upper
3. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.
The instruction set of the S25FL064K consists of thirty five basic instructions that are fully controlled through
the SPI bus (see
Select (CS#). The first byte of data clocked into the SI input provides the instruction code. Data on the SI
input is sampled on the rising edge of clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data
bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the
rising edge of edge CS#. Clock relative timing diagrams for each instruction are included in the figures below.
All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or
Erase must complete on a byte boundary (CS# driven high after a full 8-bits have been clocked) otherwise the
instruction will be ignored. This feature further protects the device from inadvertent writes. Additionally, while
the memory is being programmed or erased, or when the Status Register is being written, all instructions
except for Read Status Register will be ignored until the program or erase cycle has completed.
SEC
X
0
0
0
0
0
0
0
0
0
0
0
0
X
1
1
1
1
1
1
1
1
TB
X
X
Status Register
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
BP2
Table 7.3
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
1
0
0
0
1
(1)
BP1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
Table 6.3 Status Register Memory Protection (CMP = 1)
to
Table 7.5 on page
BP0
D a t a
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
X
1
0
1
X
Protected Block(s)
S25FL064K
16 thru 127
32 thru 127
64 thru 127
0 thru 127
0 thru 125
0 thru 123
0 thru 119
0 thru 111
2 thru 127
4 thru 127
8 thru 127
0 thru 127
0 thru 127
0 thru 127
0 thru 127
0 thru 127
0 thru 127
0 thru 127
0 thru 127
S h e e t
0 thru 95
0 thru 63
NONE
21). Instructions are initiated with the falling edge of Chip
( P r e l i m i n a r y )
S25FL064K (64 MBit) Memory Protection
Protected Addresses
000000h – 7DFFFFh
000000h – 7BFFFFh
000000h – 7FEFFFh
000000h – 7FDFFFh
000000h – 7FBFFFh
000000h – 7FFFFFh
000000h – 77FFFFh
000000h – 6FFFFFh
000000h – 5FFFFFh
000000h – 3FFFFFh
020000h – 7FFFFFh
040000h – 7FFFFFh
080000h – 7FFFFFh
100000h – 7FFFFFh
200000h – 7FFFFFh
400000h – 7FFFFFh
000000h – 7F7FFFh
001000h – 7FFFFFh
002000h – 7FFFFFh
004000h – 7FFFFFh
008000h – 7FFFFFh
NONE
S25FL064K_00_02 September 16, 2010
Protected
8,064 KB
7,936 KB
7,680 KB
8,064 KB
7,936 KB
7,680 KB
8,188 KB
8,184 KB
8,176 KB
8,160 KB
8,188 KB
8,184 KB
8,176 KB
8,160 KB
Density
NONE
8 MB
7 MB
5 MB
4 MB
7 MB
5 MB
4 MB
(3)
Protected Portion
L – 2047/2048
L – 1023/1024
L – 2047/2048
L – 1023/1024
Lower 63/64
Lower 31/32
Lower 15/16
Upper 63/64
Upper 31/32
Upper 15/16
L – 511/512
L – 255/256
L – 511/512
L – 255/256
Lower 7/8
Lower 3/4
Lower 1/2
Upper 7/8
Upper 3/4
Upper 1/2
NONE
ALL
(2)