S25FL064K Meet Spansion Inc., S25FL064K Datasheet - Page 32

• Manufacturer Part Number: S25FL064K
• Description: 64-mbit Cmos 3.0 Volt Flash Memory With 80-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

7.12
32
Word Read Quad I/O (E7h)
CLK
The Word Read Quad I/O (E7h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that
the lowest Address bit (A0) must equal 0 and only two Dummy clock are required prior to the data output. The
Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP)
directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Word
Read Quad I/O Instruction.
Word Read Quad I/O with “Continuous Read Mode”
The Word Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in
(M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the
first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should
be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after CS# is
raised and then lowered) does not require the E7h instruction code, as shown in
the instruction sequence by eight clocks and allows the Read address to be immediately entered after CS# is
asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after CS# is
raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A
“Continuous Read Mode” Reset instruction can also be used to reset (M7-0) before issuing normal
instructions (see
IO1
IO3
CS#
IO0
IO2
Mode 3
Mode 0
Figure 7.14 Word Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4 ≠10)
0
Section 7.16, Continuous Read Mode Reset (FFh or FFFFh) on page
1
Instruction (E7h)
2
3
4
D a t a
5
6
S25FL064K
7
S h e e t
4
6
A23-16
5
7
8
3
0
2
1
9
6
4
5
7
10
A15-8
2
3
0
1
( P r e l i m i n a r y )
11 12 13 14
4
5
6
7
A7-0
2
0
1
3
4
5
6
7
M7-0
1
2
3
0
15
S25FL064K_00_02 September 16, 2010
Dummy
16 17 18
Figure
6
7
5
4
Byte 1
7.14. The upper nibble of the
Figure
1
2
3
0
19 20 21 22
IO Switches from
Input to Output
6
Byte 2
4
5
7
37).
7.15. This reduces
1
2
3
0
Byte 3
4
6
5
7
0
1
2
3
23
4
5
6
7
3