S25FL128K Meet Spansion Inc., S25FL128K Datasheet - Page 16

• Manufacturer Part Number: S25FL128K
• Description: 128-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

6.2
16
Instructions
Notes:
1. X = don’t care.
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.
The instruction set of the S25FL128K consists of thirty five basic instructions that are fully controlled through
the SPI bus (see
Select (CS#). The first byte of data clocked into the SI input provides the instruction code. Data on the SI
input is sampled on the rising edge of clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data
bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the
rising edge of edge CS#. Clock relative timing diagrams for each instruction are included in the figures below.
All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or
Erase must complete on a byte boundary (CS# driven high after a full 8-bits have been clocked) otherwise the
instruction will be ignored. This feature further protects the device from inadvertent writes. Additionally, while
the memory is being programmed or erased, or when the Status Register is being written, all instructions
except for Read Status Register will be ignored until the program or erase cycle has completed.
SEC
X
0
0
0
0
0
0
0
0
0
0
0
0
X
1
1
1
1
1
1
1
1
TB
X
X
Status Register
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
BP2
Table 6.6
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
1
0
0
0
1
(1)
BP1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
Table 6.3 Status Register Memory Protection (CMP = 1)
to
Table 6.8 on page
BP0
D a t a
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
X
1
0
1
X
Protected Block(s)
S25FL128K
128 thru 255
16 thru 255
32 thru 255
64 thru 255
0 thru 255
0 thru 251
0 thru 247
0 thru 239
0 thru 223
0 thru 191
0 thru 127
4 thru 255
8 thru 255
0 thru 255
0 thru 255
0 thru 255
0 thru 255
0 thru 255
0 thru 255
0 thru 255
0 thru 255
S h e e t
None
19). Instructions are initiated with the falling edge of Chip
S25FL128K (128 Mbit) Memory Protection
( P r e l i m i n a r y )
Protected Addresses
000000h – FFEFFFh
000000h – FFDFFFh
000000h – FFBFFFh
001000h – FFFFFFh
002000h – FFFFFFh
004000h – FFFFFFh
008000h – FFFFFFh
000000h - FBFFFFh
000000h – F7FFFFh
000000h - EFFFFFh
000000h - DFFFFFh
000000h - BFFFFFh
000000h – FF7FFFh
000000h - FFFFFFh
000000h - 7FFFFFh
040000h - FFFFFFh
080000h - FFFFFFh
100000h - FFFFFFh
200000h - FFFFFFh
400000h - FFFFFFh
800000h - FFFFFFh
None
S25FL128K_00_02 April 1, 2011
Protected
16,128 kB
15,872 kB
16,128 kB
15,872 kB
16,380 kB
16,376 kB
16,368 kB
16,352 kB
16,380 kB
16,376 kB
16,368 kB
16,352 kB
Density
16 MB
15 MB
14 MB
12 MB
15 MB
14 MB
12 MB
8 MB
8 MB
None
(2)
Protected Portion
Lower - 4095/4096
Lower - 2047/2048
Lower - 1023/1024
Upper - 4095/4096
Upper - 2047/2048
Upper -1023/1024
Lower - 511/512
Upper - 511/512
Lower 63/64
Lower 31/32
Lower 15/16
Upper 63/64
Upper 31/32
Upper 15/16
Lower 7/8
Lower 3/4
Lower 1/2
Upper 7/8
Upper 3/4
Upper 1/2
None
All