S25FL128K Meet Spansion Inc., S25FL128K Datasheet - Page 38

• Manufacturer Part Number: S25FL128K
• Description: 128-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

38
6.2.23
Erase / Program Suspend (75h)
for a time duration of t
progress, the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The
BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept
other instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the
Status Register is cleared to 0. The Chip Erase instruction will not be executed if any page is protected by the
Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see
(CMP = 0) on page
The Erase/Program Suspend instruction “75h”, allows the system to interrupt a Sector or Block Erase
operation or a Page Program operation and then read from or program/erase data to, any other sectors or
blocks. The Erase/Program Suspend instruction sequence is shown in
Instruction Sequence on page
The Write Status Register instruction (01h) and Erase instructions (20h, 52h, D8h, C7h, 60h, 44h) are not
allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase operation. If
written during the Chip Erase operation, the Erase Suspend instruction is ignored. The Write Status Register
instruction (01h) and Program instructions (02h, 32h, 42h) are not allowed during Program Suspend.
Program Suspend is valid only during the Page Program or Quad Page Program operation.
The Erase/Program Suspend instruction “75h” will be accepted by the device only if the SUS bit in the Status
Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase or a Page Program operation
is on-going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the Suspend instruction will be ignored by
the device. A maximum of time of “t
suspend the erase or program operation. The BUSY bit in the Status Register will be cleared from 1 to 0
within “t
Suspend. For a previously resumed Erase/Program operation, it is also required that the Suspend instruction
“75h” is not issued earlier than a minimum of time of “t
Unexpected power off during the Erase/Program suspend state will reset the device and release the suspend
state. SUS bit in the Status Register will also reset to 0. The data within the page, sector or block that was
being suspended may become corrupted. It is recommended for the user to implement system design
techniques against the accidental power interruption and preserve data integrity during erase/program
suspend state.
SUS
” and the SUS bit in the Status Register will be set from 0 to 1 immediately after Erase/Program
15).
CLK
CS#
SO
SI
CE
.
See AC Electrical Characteristics on page 54.
Figure 6.27 Chip Erase Instruction Sequence Diagram
Mode 3
Mode 0
39.
D a t a
SUS
”
S25FL128K
(See AC Electrical Characteristics on page
0
S h e e t
1
Instruction (C7h/60h)
High Impedance
2
SUS
( P r e l i m i n a r y )
3
” following the preceding Resume instruction “7Ah”.
4
Table 6.2, Status Register Memory Protection
5
Figure 6.28, Erase/Program Suspend
6
While the Chip Erase cycle is in
7
S25FL128K_00_02 April 1, 2011
Mode 3
Mode 0
54.) is required to