S25FL008A Meet Spansion Inc., S25FL008A Datasheet - Page 12

• Manufacturer Part Number: S25FL008A
• Description: 8-megabit Cmos 3.0 Volt Flash Memory With 50 Mhz Spi Bus Interface
• Manufacturer: Meet Spansion Inc.

7.6
7.7
12
Data Protection Modes
Hold Mode (HOLD#)
Spansion SPI Flash memory devices provide the following data protection methods:
The Hold input (HOLD#) stops any serial communication with the device, but does not terminate any Write
Status Register, program or erase operation that is currently in progress.
The Hold mode starts on the falling edge of HOLD# if SCK is also low (see
use). If the falling edge of HOLD# does not occur while SCK is low, the Hold mode begins after the next falling
edge of SCK (non-standard use).
The Hold mode ends on the rising edge of HOLD# signal (standard use) if SCK is also low. If the rising edge
of HOLD# does not occur while SCK is low, the Hold mode ends on the next falling edge of CLK (non-
standard use) See
The SO output is high impedance, and the SI and SCK inputs are ignored (don’t care) for the duration of the
Hold mode.
CS# must remain low for the entire duration of the Hold mode to ensure that the device internal logic remains
unchanged. If CS# goes high while the device is in the Hold mode, the internal logic is reset. To prevent the
device from reverting to the Hold mode when device communication is resumed, HOLD# must be held high,
followed by driving CS# low.
BP2
The Write Enable (WREN) command: Must be written prior to any command that modifies data. The
WREN command sets the Write Enable Latch (WEL) bit. The WEL bit resets (disables writes) on power-up
or after the device completes the following commands:
Software Protected Mode (SPM): The Block Protect (BP2, BP1, BP0) bits define the section of the
memory array that can be read but not programmed or erased.
ranges of protected areas that are defined by Status Register bits BP2:BP0.
Hardware Protected Mode (HPM): The Write Protect (W#) input and the Status Register Write Disable
(SRWD) bit together provide write protection.
Clock Pulse Count: The device verifies that all program, erase, and Write Status Register commands
consist of a clock pulse count that is a multiple of eight before executing them.
0
0
0
0
1
1
1
1
– Page Program (PP)
– Sector Erase (SE)
– Bulk Erase (BE)
– Write Disable (WRDI)
– Write Status Register (WRSR)
Block Protect Bits
Status Register
BP1
0
0
1
1
0
0
1
1
BP0
0
1
0
1
0
1
0
1
Figure
F0000h–FFFFFh
E0000h–FFFFFh
C0000h–FFFFFh
80000h–FFFFFh
00000h–FFFFFh
00000h–FFFFFh
00000h–FFFFFh
Address Range
7.1.
Protected
None
Table 7.1 S25FL008A Protected Area Sizes
S25FL008A
(2) SA15:SA14
(4) SA15:SA12
(16) SA15:SA0
(16) SA15:SA0
(16) SA15:SA0
D a t a
(8) SA15:SA8
Protected
(1) SA15
Sectors
(0)
Memory Array
S h e e t
00000h–DFFFFh
00000h–FFFFFh
00000h–EFFFFh
00000h–BFFFFh
Address Range
00000h–7FFFFh
Unprotected
Table 7.1
None
None
None
Figure 7.1 on page
shows the sizes and address
S25FL008A_00_B2 June 29, 2007
Unprotected
SA15:SA0
SA14:SA0
SA13:SA0
SA11:SA0
SA7:SA0
Sectors
None
None
None
13, standard
Total Memory
Protected
Portion of
Area
1/16
1/8
1/4
1/2
All
All
All
0