S25FL008A Meet Spansion Inc., S25FL008A Datasheet - Page 17

• Manufacturer Part Number: S25FL008A
• Description: 8-megabit Cmos 3.0 Volt Flash Memory With 50 Mhz Spi Bus Interface
• Manufacturer: Meet Spansion Inc.

9.5
9.6
June 29, 2007 S25FL008A_00_B2
Write Disable (WRDI)
Read Status Register (RDSR)
The Write Disable (WRDI) command (see
a 0, which disables the device from accepting a Write Status Register, program, or erase command. The host
system must first drive CS# low, write the WRDI command, and then drive CS# high.
Any of following conditions resets the WEL bit:
The Read Status Register (RDSR) command outputs the state of the Status Register bits.
the status register bits and their functions.
The RDSR command may be written at any time, even while a program, erase, or Write Status Register
operation is in progress. The host system should check the Write In Progress (WIP) bit before sending a new
command to the device if an operation is already in progress.
sequence, which also shows that it is possible to read the Status Register continuously until CS# is driven
high.
Power-up
Write Disable (WRDI) command completion
Write Status Register (WRSR) command completion
Page Program (PP) command completion
Sector Erase (SE) command completion
Bulk Erase (BE) command completion
Bit
7
6
5
4
3
2
1
0
Status Register Bit
SRWD
WEL
BP2
BP1
BP0
WIP
—
—
D a t a
Figure 9.5 Write Disable (WRDI) Command Sequence
SCK
CS#
SO
SI
Status Register Write Disable
Mode 3
Mode 0
Hi-Z
Write Enable Latch
Write in Progress
Table 9.2 S25FL008A Status Register
S h e e t
Bit Function
Block Protect
S25FL008A
—
—
Figure 9.5 on page
0 1 2 3 4 5 6 7
Command
1 = Protects when W# is low
0 = No protection, even when W# is low
Not used
Not used
000–111 = Protects upper half of address range in 5 sizes. See
Table 7.1 on page
1 = Device accepts Write Status Register, program, or erase
commands
0 = Ignores Write Status Register, program, or erase commands
1 = Device Busy. A Write Status Register, program, or erase
operation is in progress
0 = Ready. Device is in standby mode and can accept commands.
Figure 9.6
17) resets the Write Enable Latch (WEL) bit to
12.
shows the RDSR command
Description
Table 9.2
shows
17