EMD56324P Emlsi Inc., EMD56324P Datasheet - Page 9
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EMD56324P
Manufacturer Part Number
EMD56324P
Description
256m 8m X 32 Mobile Ddr Sdram
Manufacturer
Emlsi Inc.
Datasheet
1.EMD56324P.pdf
(45 pages)
Table 8: OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
DQ output access time from CK/CKB
DQS output access time from CK/CKB
Clock high-level width
Clock low-level width
Clock half period
Clock cycle time
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input pulse width
Address and control input setup time
Address and control input hold time
Address and control input pulse width
DQ & DQS low-impedance time from CK/CKB
DQ & DQS high-impedance time from CK/CKB
DQS - DQ skew
DQ / DQS output hold time from DQS
Data hold skew factor
Write command to 1st DQS latching transition
DQS input high-level width
DQS input low-level width
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
MODE REGISTER SET command period
Write preamble setup time
Write postamble
Write preamble
Parameter
CL = 3
CL = 2
t
t
t
WPRES
t
DQSCK
t
t
t
Sym-
t
t
t
WPRE
DQSQ
t
DQSS
DQSH
t
WPST
DQSL
t
DIPW
t
bol
t
t
t
QHS
MRD
t
t
t
t
t
t
DSS
DSH
IPW
t
t
t
CH
DH
QH
AC
CL
HP
CK
DS
HZ
LZ
IS
IH
t
(t
HP
CL
0.45
0.45
0.75
0.25
Min
min
0.6
0.6
1.8
1.1
1.1
2.6
1.0
0.4
0.4
0.2
0.2
0.4
12
-t
2
2
6
2
0
,t
QHS
9
CH
)
-60
Max
0.55
0.55
0.65
1.25
100
100
0.5
0.6
0.6
0.6
5
5
5
t
(t
HP
CL
0.45
0.45
0.75
0.75
0.75
0.25
Min
min
2.5
2.5
7.5
2.5
1.3
1.3
2.6
1.0
0.4
0.4
0.2
0.2
0.4
256M: 8M x 32 Mobile DDR SDRAM
12
-t
2
0
,t
QHS
CH
)
-75
Max
0.55
0.55
0.75
1.25
100
100
6.0
6.0
6.0
0.6
0.6
0.6
0.6
EMD56324P
Unit
t
t
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
Preliminary
Note
4,5
4,5
3
1
1
Rev 0.0