EMD12164P Emlsi Inc., EMD12164P Datasheet - Page 2

• Manufacturer Part Number: EMD12164P
• Description: 512m 32m X 16 Mobile Ddr Sdram
• Manufacturer: Emlsi Inc.

512M : 32M x 16bit Mobile DDR SDRAM
Table 1: ORDERING INFORMATION
NOTE :
1. EMLSI is not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.
FEATURES
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Please contact to the memory marketing team in EMLSI when considering the use of a product contained herein for any specific purpose,
such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
1.8V power supply, 1.8V I/O power
LVCMOS compatible with multiplexed address.
Double-data-rate architecture; two data transfers per clock
Bidirectional data strobe(DQS)
Four banks operation.
MRS cycle with address key programs.
Differential clock inputs(CK and CKB).
EMRS cycle with address key programs.
Internal auto TCSR
Deep power-down(DPD) mode.
DM for write masking only.
Auto refresh and self refresh modes.
64
Operating temperature range (-25
cycle
(Temperature Compensated Self Refresh)
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PASR(Partial Array Self Refresh).
DS (Driver Strength)
CAS latency (2, & 3).
Burst length (2, 4, & 8).
Burst type (Sequential & Interleave).
EMD12164P-60(DDR332)
EMD12164P-75(DDR266)
¢
refresh period (8K cycle).
Part No.
£
166 (CL3), 111 (CL2)
~ 85
133 (CL3), 83 (CL2)
£
).
Max Freq.
2
GENERAL DESCRIPTION
rate Dynamic RAM. Each 134,217,728 bits bank is organized as
8,192 rows by 1024columns by 16 bits, fabricated with EMLSI’s
high performance CMOS technology.
speed operation. The double data rate architecture is essentially
a 2n-prefetch architecture with an interface designed to transfer
two data words per clock cycle at the I/O balls.
and programmable latencies allow the same device to be useful
for a variety of high bandwidth and high performance memory
system applications.
This EMD12164P is 536,870,912 bits synchronous double data
This device uses a double data rate architecture to achieve high-
Range of operating frequencies, programmable burst lengths
Interface
LVCMOS
512M: 32M x 16 Mobile DDR SDRAM
Wafer Biz.
Package
EMD12164P
Preliminary
Remark
Rev 0.0