cs4228a Cirrus Logic, Inc., cs4228a Datasheet - Page 23
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cs4228a
Manufacturer Part Number
cs4228a
Description
24-bit, 96 Khz Surround Sound Codec
Manufacturer
Cirrus Logic, Inc.
Datasheet
1.CS4228A.pdf
(32 pages)
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DACPDN12
DACPDN34
DACPDN56
5.4
MUTL, MUTR
HPF
HPFZ
5.5
MUT6 - MUT1
RMP1:0
MUTL
MUT6
7
0
7
1
ADC Control
DAC Mute1 Control
Address 0x03
Address 0x04
MUTR
MUT5
coming
attenuated to its maximum value (90.5 dB). When deasserted, the corresponding DAC attenu-
ation value returns to the value stored in the corresponding Digital Volume Control register. The
attenuation value is ramped up and down at the rate specified by RMP1:0.
Power down the analog section of DAC 1 and 2
Power down the analog section of DAC 3 and 4
Power down the analog section of DAC 5 and 6
ADC left and right channel mute control
Mute control for DAC6 - DAC1 respectively. When asserted, the corresponding DAC is digitally
*0 -
1 -
*0 -
1 -
*0 -
1 -
*0 -
1 -
ADC DC offset removal. See “High Pass Filter” for more information
*0 -
1 -
ADC DC offset averaging freeze. See “High Pass Filter” for more information
*0 -
1 -
0 -
*1 -
Attenuation ramp rate.
*0 -
1 -
2 -
3 -
6
0
6
1
Normal
Power down DAC 1 and 2.
Normal
Power down DAC 3 and 4.
Normal
Power down DAC 5 and 6.
Normal
Selected ADC output muted
Enabled
Disabled
Normal. The DC offset average is dynamically calculated and subtracted from in-
ADC data.
Freeze. The DC offset average is frozen at the current value and subtracted from
incoming ADC data. Allows passthru of DC information.
Normal output level
Selected DAC output fully attenuated.
0.5 dB change per 4 LRCKs
0.5 dB change per 8 LRCKs
0.5 dB change per 16 LRCKs
0.5 dB change per 32 LRCKs
MUT4
HPF
5
0
5
1
MUT3
HPFZ
4
0
4
1
MUT2
3
0
3
1
MUT1
2
0
2
1
RESERVED
RMP1
1
0
1
0
CS4228A
RMP0
0
0
0
0
23