cs4239 Cirrus Logic, Inc., cs4239 Datasheet - Page 24

• Manufacturer Part Number: cs4239
• Description: Crystalclear? Ortable Isa Audio System Logic
• Manufacturer: Cirrus Logic, Inc.

FMS2-FMS0
This register sets the power up defaults for these fea-
tures. After power-up, I16 may be used to control the
DSP serial port, and I26 may be used to control the
Mono Input.
MIA
SPE
SF1,0
24
HW Config. Byte 10: FM Volume Scaling,
Default = 00100000
HW Config. Byte 14: Mono & DSP Port
Control, Default = 10000000
MIM
D7
D7
res
FMS2
D6
D6
res
FMS1
D5
D5
res
FM Volume Scaling relative to wave-
table digital input. These bits set the
default FM volume level relative to
the CS9236 wavetable interface
port. Once initialized, these bits can
be controlled through X19. These
bits are provided for backwards com-
patibility with previous chips.
010 - 0 dB
011 - +6 dB
100 - -12 dB
101 - -6 dB
110 - +12 dB
111 - +18 dB
Mono Input Attenuate. When set, the
MIN input is attenuated 9 dB. When
clear, the MIN volume is 0 dB.
DSP Serial Port Enable. When set,
the DSP serial port is enabled.
DSP Serial Port Format. Selects the
format of the serial port once en-
abled by SPE. See the DSP Serial
Audio Data Port section for more de-
tails.
00 - 64-bit enhanced.
01 - 64-bit.
10 - 32 bit.
11 - ADC/DAC.
FMS0
D4
D4
res
SF1
D3
D3
res
SF0
D2
D2
res
SPE
D1
D1
res
MIA
D0
D0
res
MIM
EC7-EC0
This register sets the power up defaults for these fea-
tures. After power-up, X18 may be used to control all
bits except EECS.
ZVEN
PSH
DSPD1
3DEN
AUX1R
HW Config. Byte 15: E
Default = xxxxxxxx
HW Config. Byte 16: Global Config. Byte 2
Default = 00000000
EC7
D7
D7
res
EECS AUX1R 3DEN
EC6
D6
D6
CrystalClear Portable ISA Audio System
D5
EC5
D5
Mono In mute. When set, the MIN
analog input is muted. When clear,
MIN is mixed into the output mixer
at a level set by MIA.
the first byte of the size (after
55h/BBh) and ends with the last pro-
grammed byte of the E
valid if EECS in Hardware Configura-
tion Byte 16 is set.
ZVPORT Enable. When set, the
ZVPORT pins are enabled and se-
lected as input to DAC2. While the
ZVPORT is enabled, no other input
to DAC2 is allowed (synthesizers or
DSP).
Playback Sample Hold. When set, the
last sample is held in DAC1 when
PEN is cleared. When clear, zero is
sent to DAC1 when PEN is cleared.
DSP port controls DAC1. When set,
the serial DSP port controls DAC1 in-
stead of the ISA playback FIFO.
sound is enabled on L/ROUT.
AUX1 Remap. When set, writes to
I18/19 (DAC2 volume) also control
the AUX1 volume. When clear,
I18/19 control DAC2 volume and
I2/3 control AUX1 volume. This bit
provides some backwards compatibil-
E
3D Sound Enable. When set, 3D
2
PROM checksum byte. Starts with
EC4
D4
D4
TM
2
PROM Checksum
DSPD1 PSH
EC3
D3
D3
EC2
D2
D2
2
PROM. Only
ZVEN
EC1
D1
D1
CS4239
DS253PP2
EC0
D0
D0
res