cs4239 Cirrus Logic, Inc., cs4239 Datasheet - Page 83

• Manufacturer Part Number: cs4239
• Description: Crystalclear? Ortable Isa Audio System Logic
• Manufacturer: Cirrus Logic, Inc.

ISA Bus Interface Pins
SA<11:0> - System Address Bus, Inputs
SA<15:12> - Upper System Address Bus, Inputs
SD<7:0> - System Data Bus, Bi-directional, 24 mA drive
AEN - Address Enable, Input
IOR - Read Command Strobe, Input
IOW - Write Command Strobe, Input
IOCHRDY - I/O Channel Ready, Open Drain Output, 8 mA drive
DRQ<A,B,C> - DMA Requests, Outputs, 24 mA drive
DS253PP2
These signals are decoded during I/O cycles to determine access to the various functional
blocks within the part as defined by the configuration data written during a Plug and Play
configuration sequence.
These signals are multi-function pins, shared with the CDROM, that default to the upper
address bits SA12 through SA15. These pins are generally used for motherboard designs that
want to eliminate address decode aliasing. Using these pins as upper address bits forces the part
to only accept valid address decodes when A12-A15 = 0. If these pins are not used for address
decodes or for CDROM support, they should be tied to SGND. These pins are forced to the
CDROM interface when a 10 k resistor is placed on pin MCLK/SCLK to SGND.
These signals are used to transfer data to and from the part.
This signal indicates whether the current bus cycle is an I/O cycle or a DMA cycle. This signal
is low during an I/O cycle and high during a DMA cycle.
This active low signal defines a read cycle to the part. The cycle may be a register read or a
read from the part’s DMA registers.
This active low signal indicates a write cycle to the part. The cycle may be a write to a control
register or a DMA register.
This signal is driven low by the part during ISA bus cycles in which the part is not able to
respond within a minimum cycle time. IOCHRDY is forced low to extend the current bus
cycle. The bus cycle is extended until IOCHRDY is brought high.
These active high outputs are generated when the part is requesting a DMA transfer. This signal
remains high until all the bytes have been transferred as defined by the current transfer data
type. The DRQ<A,B,C> outputs must be connected to 8-bit DMA channel request signals only.
The defaults on the ISA bus are DRQA = DRQ0, DRQB = DRQ1, and DRQC = DRQ3. The
defaults can be changed by modifying the Hardware Resource data.
CrystalClear Portable ISA Audio System
TM
CS4239
83