cs4237b Cirrus Logic, Inc., cs4237b Datasheet - Page 33

• Manufacturer Part Number: cs4237b
• Description: Crystalclear Advanced Audio System With 3d Sound
• Manufacturer: Cirrus Logic, Inc.

IA3-IA0
IA4
TRD
MCE
INIT
Immediately after RESET (and once the WSS
Codec has left the INIT state), the state of this
register is: 010x0000 (binary - where ’x’ indi-
cates unknown).
DS213PP4
Index Address Register
(WSSbase+0, R0)
INIT
D7
MCE
D6
TRD
D5
Index Address: These bits define the
address of the indirect register ac-
cessed by the Indexed Data register
(R1). These bits are read/write.
Allows access to indirect registers 16
served and must be written as zero.
Transfer Request Disable: This bit,
when set, causes DMA transfers to
cease when the INT bit of the Status
Register (R2) is set. Independent for
playback and capture interrupts.
0 - Transfers Enabled (playback and
1 - Transfers Disabled (playback and
Mode Change Enable: This bit must
be set whenever the current mode
of the WSS Codec is changed. The
Data Format (I8, I28) and Interface
Configuration (I9) registers CANNOT
be changed unless this bit is set.
The exceptions are CEN and PEN
which can be changed "on-the-fly".
The DAC output is muted when
MCE is set.
WSS Codec Initialization: This bit is
read as 1 when the Codec is in a
state in which it cannot respond to
parallel interface cycles. This bit is
read-only.
- 31. In MODE 1, this bit is re-
capture DRQs occur uninhibited)
capture DRQ only occur if INT bit
is 0)
D4
IA4
D3
IA3
D2
IA2
D1
IA1
D0
IA0
During initialization and software power down
(PM1,0 = 01), this register CANNOT be written
and always reads 10000000 (80h)
ID7-ID0
During initialization and software power down
of the WSS Codec, this register can NOT be
written and is always read 10000000 (80h)
INT
PRDY
Indexed Data Register
(WSSbase+1, R1)
Status Register
(WSSbase+2, R2, Read Only)
CU/L
D7
D7
ID7
CL/R
D6
D6
ID6
CRDY
D5
D5
ID5
Indexed Data register: These bits are
the indirect register referenced by
the Indexed Address register (R0).
Interrupt Status: This indicates the
status of the internal interrupt logic
of the WSS Codec. This bit is
cleared by any write of any value to
this register. The IEN bit of the Pin
Control register (I10) determines
whether the state of this bit is re-
flected on the IRQ pin assigned to
the WSS Codec.
Read States
0 - Interrupt inactive
1 - Interrupt active
Playback Data Ready. The Playback
Data register (R3) is ready for more
data. This bit would be used when di-
rect programmed I/O data transfers
are desired.
0 - Data still valid. Do not overwrite.
1 - Data stale. Ready for next host
data write value.
SER
D4
ID4
D4
PU/L
D3
D3
ID3
PL/R
D2
D2
ID2
PRDY
CS4237B
D1
D1
ID1
D0
ID0
D0
INT
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