cs4237b Cirrus Logic, Inc., cs4237b Datasheet - Page 42

• Manufacturer Part Number: cs4237b
• Description: Crystalclear Advanced Audio System With 3d Sound
• Manufacturer: Cirrus Logic, Inc.

Playback Lower Base (I15)
Default = 00000000
PLB7-PLB0
Alternate Feature Enable I (I16)
Default = 00000000
DACZ
SPE
SF1,SF0
42
PLB7
OLB
D7
D7
PLB6
D6
D6
TE
CMCE PMCE
PLB5
D5
D5
which was written. The Current
Count registers cannot be read.
When set for MODE 1 or SDC, this
register is used for both the Play-
back and Capture Base registers.
Lower Base Bits: This register is the
lower byte which represents the 8
least significant bits of the 16-bit
Playback Base register. Reads from
this register return the same value
which was written. When set for
MODE 1 or SDC, this register is
used for both the Playback and Cap-
ture Base registers.
DAC Zero: This bit will force the out-
put of the playback channel to AC
zero when an underrun error occurs
1 - Go to center scale
0 - Hold previous valid sample
DSP Serial Port Enable. When
set, audio data from the ADCs is
sent out SDOUT and audio data
from SDIN is sent to the DACs.
MCE in R0 must be set to change
this bit.
1 - Enable serial port
0 - Disable serial port. ISA Bus
Serial Format. Selects the format of
the serial port when enabled by
SPE. MCE in R0 must be set to
change these bits.
0 - 64-bit enhanced. Figure 9.
used for audio data.
PLB4
D4
D4
PLB3
SF1
D3
D3
PLB2
SF0
D2
D2
PLB1
SPE
D1
D1
DACZ
PLB0
D0
D0
PMCE
CMCE
TE
OLB
Alternate Feature Enable II (I17)
Default = 0000x000
HPF
XTALE
res
TEST
D7
TEST
D6
TEST
1 - 64-bit. Figure 10.
2 - 32-bit. Figure 11.
3 - ADC/DAC. Figure 12.
When set, it allows modification of
the stereo/mono and audio data for-
mat bits (D7-D4) for the playback
channel, I8. MCE in R0 must be
used to change the sample fre-
quency.
Capture Mode Change Enable.
When set, it allows modification of
the stereo/mono and audio data for-
mat bits (D7-D4) for the capture
channel, I28. MCE in R0 must be
used to change the sample fre-
quency in I8.
Timer Enable: This bit, when set, will
enable the timer to run and interrupt
the host at the specified frequency
in the timer registers.
wards compatibility with the CS4236.
This bit does nothing on this chip.
High Pass Filter: This bit enables a
DC-blocking high-pass filter in the
digital filter of the ADC. This filter
forces the ADC offset to 0.
0 - disabled
1 - enabled
Crystal Enable. Provided for back-
wards compatibility with the
CS4231A. This bit does nothing on
the this part.
Reserved. Must write 0. Could read
as 0 or 1.
Playback Mode Change Enable.
Output Level Bit: Provided for back-
D5
TEST
D4
APAR
D3
D2
res
XTALE
CS4237B
D1
DS213PP4
HPF
D0