cs4215 Cirrus Logic, Inc., cs4215 Datasheet - Page 17
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cs4215
Manufacturer Part Number
cs4215
Description
16-bit Multimedia Audio Codec
Manufacturer
Cirrus Logic, Inc.
Datasheet
1.CS4215.pdf
(52 pages)
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DS76F2
periods for FSYNC and
receive SCLK and FSYNC
Wait at least 12 SCLK
Set external controller to
SCLK to three-state
from the codec
Transmit/receive data with attenuated outputs
Y
Y
and muted speaker for 194 FSYNC cycles
Read back and verify control information.
while codec executes offset calibration
Figure 11. Control Mode Flow Chart
Send valid control information
Set CLB=1 and send at least
Transmit/receive audio data
with desired level settings
N
Set external controller to
two more frames of valid
Mute the speaker output
drive SCLK and FSYNC
Master mode & ITS=0?
Codec programmed for
Mask off reserved bits
maximum attenuation
Lower output level to
control information
Poll for CLB=0?
programmed for
Master mode?
into the codec
Set D/C high.
Set D/C low
with CLB=0
CLB=0?
Is codec
Y
N
Y
N
1
2
N
2
1
This is a software design choice,
not a run-time conditional branch.
This will cause the codec to
ignore any further bus activity.
The SDOUT pin will be held in
the high impedance state after
transmitting 1 frame with CLB=1
Send valid control information
with CLB=0
n = n - 1
n = 0?
n = 5
Y
CS4215
N
17