cs4215 Cirrus Logic, Inc., cs4215 Datasheet - Page 22

• Manufacturer Part Number: cs4215
• Description: 16-bit Multimedia Audio Codec
• Manufacturer: Cirrus Logic, Inc.

A-Law: 2Ah
u-Law:
of 128 (80 Hex) is considered analog zero for
the 8-bit unsigned format.
A non-linear coding scheme is used for the com-
panded formats as shown in Figure
scheme is compatible with CCITT G.711. Com-
panding uses more precision at lower amplitudes
at the expense of less precision at higher ampli-
tudes.
signal levels and A-Law is equivalent to 12 bits.
This low-level dynamic range is obtained at the
expense of large-signal dynamic range which, for
both
The CS4215 internally operates at 16 bits. The
companded data is expanded to the upper 13
Data Time Slot 5, Output Setting
22
LO5-0
LE
HE
+FS
-FS
BIT
0
00h
-Law and A-Law, is equivalent to 6 bits.
Figure 14. Companded Data Formats
-Law is equivalent to 13 bits at low
Left Channel Output
Attenuation Setting
Line Output Enable
Headphone Output
Enable
15h
3Fh
Reset (R)
Register
NAME
DIGITAL CODE
55h/D5h
7Fh/FFh
HE
D7
0
1 1 1 1 1 1
95h
BFh
LE
D6
0
0
1
0
1
14.
VALUE
LO5
D5
This
1
AAh
80h
63 R 1.5dB attenuation steps. LO5 is the MSB.
LO4
R Analog line outputs off (muted).
R Headphone output off (muted).
D4
1
(12) bits for the DACs and compressed from the
upper 13 (12) bits to 8 bits for the ADCs.
Data Time Slot 1&2, Left Channel Audio Data
Time slot 1 and 2 contain audio data for the left
channel. In mono modes, only the left channel
data is used, however both the right and left
output DACs are driven. In 8-bit modes, only
time slot 1 is used for the data.
Data Time Slot 3&4, Right Channel Audio Data
Time slot 3 and 4 contains audio data for the
right channel. In mono modes, the right ADC
outputs zero and the right DAC uses the left
digital data. In 8-bit modes, only time slot 3 is
used for the data.
Figure 15 summarizes all the time slot bit alloca-
tions for the 4 data modes and for control mode.
Reset
RESET going low causes all the internal control
registers to be set to the states shown with each
register description. RESET must be brought low
and high at least once after power up. RESET
returning high causes the CS4215 to execute an
offset calibration cycle. RESET or D/C returning
high should occur at least 50 ms after the power
supply has stabilized to allow the voltage refer-
ence to settle.
Analog line outputs on.
Headphone output on.
0 = no attenuation. 111111 = -94.5dB
LO3
D3
1
LO2
D2
1
LO1
FUNCTION
D1
1
LO0
D0
1
CS4215
DS76F2